參數(shù)資料
型號(hào): SY100E404JZ
廠商: Micrel Inc
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 0K
描述: IC GATE AND/NAND QUAD 28-PLCC
標(biāo)準(zhǔn)包裝: 38
系列: 100E
邏輯類型: 與/與非門
電路數(shù): 4
輸入數(shù): 8 輸入(2,2,2,2)
施密特觸發(fā)器輸入: 無(wú)
輸出類型: 差分
電源電壓: 4.2 V ~ 5.5 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 管件
1
SY10E404
SY100E404
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
FEATURES
s Differential D and Q
s Extended 100E VEE range of –4.2V to –5.5V
s 700ps max. propagation delay
s High frequency outputs
s Internal 75K
input pull-down resistors
s Fully compatible with Motorola 10E/100E404
s Available in 28-pin PLCC package
The SY10/100E404 are 4-bit differential AND/NAND
devices. The differential operation of these devices make
them ideal for pulse shaping applications where duty cycle
skew is critical. Special design techniques were
incorporated to minimize the skew between the upper
and lower level gate inputs.
Because a negative 2-input NAND function is
equivalent to a 2-input OR function, the differential inputs
and outputs of the devices also allow for their use as
fully differential 2-input OR/NOR functions.
The output RISE/FALL times of these devices are
significantly faster than most other standard ECLinPS
devices, resulting in an increased bandwidth.
The differential inputs have clamp structures which
will force the Q output of a gate in an open input condition
to go to a LOW state. Thus, inputs of unused gates can
be left open and will not affect the operation of the rest
of the device.
QUAD DIFFERENTIAL
AND/NAND
SY10E404
SY100E404
BLOCK DIAGRAM
D0a
D0b
Q0
D1a
D1b
Q1
D2a
D2b
Q2
D3a
D3b
Q3
Pin
Function
D[0:4], D[0:4]
Differential Data Inputs
Q[0:4], Q[0:4]
Differential Data Outputs
VCCO
VCC to Output
PIN NAMES
Rev.: G
Amendment: /0
Issue Date:
March 2006
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