參數(shù)資料
型號(hào): SY100EL34LZI
廠商: MICREL INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
中文描述: 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 69K
代理商: SY100EL34LZI
1
Precision Edge
Precision Edge
SY10EL34/L
SY100EL34/L
Micrel, Inc.
M9999-031006
hbwhelp@micrel.com or (408) 955-1690
The SY10/100EL34/L are low skew
÷
2,
÷
4,
÷
8 clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
BB
output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the V
BB
output should be connected to the CLK
input and bypassed to ground via a 0.01
μ
F capacitor.
The V
BB
output is designed to act as the switching
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
Pin
Function
CLK
Differential Clock Inputs
EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0
Differential
÷
2 Outputs
Differential
÷
4 Outputs
Differential
÷
8 Outputs
Q
1
Q
2
DESCRIPTION
PIN NAMES
FEATURES
5V/3.3V
÷
2,
÷
4,
÷
8 CLOCK
GENERATION CHIP
I
3.3V and 5V power supply options
I
50ps output-to-output skew
I
Synchronous enable/disable
I
Master Reset for synchronization
I
Internal 75K
input pull-down resistors
I
Available in 16-pin SOIC package
Rev.: H
Issue Date:
Amendment: /0
March 2006
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge
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