參數(shù)資料
型號: SY100EL51ZI TR
廠商: Micrel Inc
文件頁數(shù): 1/4頁
文件大?。?/td> 0K
描述: IC FLIP FLOP DIFF CLOCK D 8-SOIC
標準包裝: 1,000
系列: 100EL
功能: 復位
類型: D 型
輸出類型: 差分
元件數(shù): 1
每個元件的位元數(shù): 1
頻率 - 時鐘: 2.8GHz
延遲時間 - 傳輸: 475ps
觸發(fā)器類型: 正,負
電源電壓: 4.2 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: SY100EL51ZITR
SY100EL51ZITR-ND
1
SY10EL51
SY100EL51
Micrel, Inc.
M9999-121205
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s 475ps propagation delay
s 2.8GHz toggle frequency
s Internal 75K
input pull-down resistors
s Available in 8-pin SOIC package
The SY10/100EL51 are differential clock D flip-flops
with reset. These devices are functionally similar to the
E151 devices, with higher performance capabilities. With
propagation delays and output transition times
significantly faster than the E151, the EL51 is ideally
suited for those applications which require the ultimate
in AC performance.
The reset input is an asynchronous, level triggered
signal. Data enters the master portion of the flip-flop
when the clock is LOW and is transferred to the slave,
and thus the outputs, upon a positive transition of the
clock. The differential clock inputs of the EL51 allow the
device to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to
maintain stability under open input (pulled down to VEE)
conditions.
FEATURES
DIFFERENTIAL
CLOCK D FLIP-FLOP
PIN NAMES
Pin
Function
R
Reset Input
D
Data Input
CLK
Clock Input
Q
Data Output
SY10EL51
SY100EL51
D
R
CLK
Q
LL
Z
L
HL
Z
H
XH
X
L
NOTE:
1. Z = LOW-to-HIGH transition.
TRUTH TABLE(1)
1
Rev.: G
Amendment: /0
Issue Date:
December 2005
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