參數(shù)資料
型號: SY100ELT21ZI
廠商: Micrel Inc
文件頁數(shù): 5/5頁
文件大?。?/td> 0K
描述: IC TRANSLATOR DIFF 8-SOIC
標準包裝: 95
系列: 100ELT
邏輯功能: 變換器
位數(shù): 1
輸入類型: PECL
輸出類型: TTL
通道數(shù): 1
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 是/無
傳輸延遲(最大): 3ns
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
Technical Note
5/17
www.rohm.com
2010.06 - Rev.A
2010 ROHM Co., Ltd. All rights reserved.
BD3813KS,BD3815KS
●Timing Chart
1) Signal Timing Conditions
·Data is read on the rising edge of the clock.
·Latch is read on the falling edge of the clock.
·The latch signal must terminate with the Low state.
*To avoid malfunction, the clock and data signals must terminate with the Low state.
Fig.1
Parameter
Symbol
Limits
Unit
Min.
Typ.
Max.
Minimum Clock Width
twc
2.0
s
Minimum Data Width
twd
2.0
s
Minimum Latch Width
twl
2.0
s
Low Hold Width
twh
2.0
s
Data Set-up Time (Data
Clock)
tsd
1.0
s
Data Hold Time ( Clock
Data )
thd
1.0
s
Latch Set-up Time ( Clock
Latch)
tsl
1.0
s
Latch Hold Time ( Data
Latch )
thl
1.0
s
Latch Low Set-up Time
ts
1.0
s
Latch Low Hold Time
th
1.0
s
2) Control Signal Voltage Conditions
Parameter
Condition
Limits
Unit
Min.
Typ.
Max.(
≤Vcc)
“H” Input Voltage
Vcc=5
7.3V
VEE=-5-7.3V
2.2
5.5
V
“L” Input Voltage
0
1.0
V
CL
(Clock)
DA
Data
Latch
thd
th
ts
tsl
thl
tsd
twc
twh
twd
twl
Data
Latch
90%
10%
90%
10%
twc
Terminate
with Low
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