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參數(shù)資料
| 型號： | SY100EP15VK4G |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V / 5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX |
| 中文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 110K |
| 代理商： | SY100EP15VK4G |
3
ECL Pro
SY100EP15V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
TRUTH TABLE
(1)
CLK0
CLK1
SEL
/EN
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
L
H
L
X
H
H
L
PIN DESCRIPTION
Pin
Pin Number
Function
1, 2, 3, 4
5, 6, 7, 8
Q0 – Q3
/Q0 – /Q3
Outputs 0 through 3: 100KEP (LV)PECL/(LV)ECL compatible differential outputs. Terminate
with 50
to V
CC
–2V. Unused output pairs may be left floating, or pulled-down with a 2k
resistor to the most negative supply. Unused single-ended outputs must have a balanced load.
For AC-coupled applications, the output stage emitter follower must have a DC current path to
ground. See “Termination” section.
9
VEE
Negative Power Supply: For PECL/LVPECL applications, connect to GND.
10
SEL
100KEP (LV)PECL/(LV)ECL Compatible 2:1 Mux Input Select Control. See “Truth Table.” The
select (SEL) pin includes an internal 75k
pull-down resistor. Default condition when left floating
is LOW, and CLK0 input is selected.
11, 12
CLK0, /CLK0
Differential (LV)PECL/(LV)ECL/HSTL Compatible Input: The inputs include an internal 75k
pull-down resistor on CLK0 and internal 75k
pull-up and pull-down on /CLK0. Default condition
for CLK0 is LOW when left floating and V
CC
/2 for /CLK0 when left floating.
Reference Output Voltage: This reference is typically used to bias the unused inverting input for
single-ended input applications, or as the termination point for AC-coupled differential input
applications. V
BB
reference value is approximately V
CC
–1.3V, and tracks Vcc 1:1. Maximum
sink/source capability for V
BB
is 0.50mA. For single ended inputs, connect to the unused input
through a 50
resistor. Decouple the V
BB
pin with a 0.01
μ
F capacitor to V
CC
.
Single-Ended (LV)PECL/(LV)ECL Compatible Input: This pin includes an internal 75k
pull-down resistor. Default condition is LOW when left floating.
13
VBB
14
CLK1
15
/EN
100KEP (LV)PECL/(LV)ECL Compatible Input: This synchronous pin controls the output state.
See “Truth Table.” To ensure proper synchronous operation, adhere to the Set-up and Hold
times, as described in the AC electrical table. When /EN pin goes HIGH, Q outputs go LOW, and
/Q outputs go HIGH on the next falling clock transition. This synchronous operation avoids any
chance of generating a runt pulse.
16
VCC
Positive Power Supply: Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors.
Note:
1.
= Negative edge.
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| SY100EP15VK4G TR | 功能描述:緩沖器和線路驅(qū)動器 3.3V/5V 1:4 PECL Fanout Buffer w/ 2:1 Mux (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY100EP15VK4I | 功能描述:IC CLOCK BUFFER MUX 4:4 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:100EP, Precision Edge®, ECL Pro™ 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY100EP16LSKI | 功能描述:IC LINE RCVR SGL DIFF 8-MSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100EP 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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