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參數(shù)資料
| 型號： | SY100EP195VTI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 100EP, ECL Pro® |
| 標(biāo)片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.05ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.05ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100EP195VTITR SY100EP195VTITR-ND |
3
ECL Pro
SY100EP195V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
D[0:9]
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
30, 31, 32, 1, 2
delay from IN to Q. Please refer to the “Ac Electrical Table” (page 7) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP195V to extend the range of delays required.
4, 5
IN, /IN
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6
VBB
Voltage Output: When using a single-ended logic source for IN and /IN, connect the
unused input of the differential pair to this pin. This pin can also re-bias AC-coupled inputs
to IN and /IN. When used, de-couple this pin to VCC through an 0.01F capacitor. Limit
current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the
“Digital
Control Logic Standard” section of the “Functional Description” to interface the D inputs to
CMOS or TTL.
8
VCF
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28
VEE
Most Negative Supply: Supply ground for PECL systems.
10
LEN
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
SETMIN
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12
SETMAX
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22
VCC
Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1F and
0.01F low ESR capacitors.
15, 14
CASCADE,
100 ECL Outputs: These outputs are used when cascading two or more SY100EP195V to
/CASCADE
extend the delay range required.
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
20, 21
Q, /Q
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
17
NC
No Connect: Leave this pin unconnected.
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