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參數(shù)資料
| 型號(hào)： | SY100EP195VTI |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | SY100EP195VTI |
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3
ECL Pro
SY100EP195V
Micrel
M0643-121504
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
D[0:9]
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the
“
Ac Electrical Table
”
(page 7) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP195V to extend the range of delays required.
4, 5
IN, /IN
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6
VBB
Voltage Output: When using a single-ended logic source for IN and /IN, connect the
unused input of the differential pair to this pin. This pin can also re-bias AC-coupled inputs
to IN and /IN. When used, de-couple this pin to V
CC
through an 0.01
μ
F capacitor. Limit
current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the
“
Digital
Control Logic Standard
”
section of the
“
Functional Description
”
to interface the D inputs to
CMOS or TTL.
8
VCF
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28
VEE
Most Negative Supply: Supply ground for PECL systems.
10
LEN
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
SETMIN
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12
SETMAX
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
Most Positive Supply: Supply ground for NECL systems. Bypass to V
EE
with 0.1
μ
F and
0.01
μ
F low ESR capacitors.
100 ECL Outputs: These outputs are used when cascading two or more SY100EP195V to
extend the delay range required.
13, 18, 19, 22
VCC
15, 14
CASCADE,
/CASCADE
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
20, 21
Q, /Q
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
17
NC
No Connect: Leave this pin unconnected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100EP195VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:100EP, ECL Pro® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP196VTG | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100EP196VTG TR | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100EP196VTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:100EP, ECL Pro® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP196VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:100EP, ECL Pro® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
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