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參數(shù)資料
| 型號： | SY100EP196VTG |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3V/5V 2.5GHz PROGRAMMABLE DELAY WITH FINE TUNE CONTROL |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| 封裝： | LEAD FREE, TQFP-32 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 628K |
| 代理商： | SY100EP196VTG |
15
ECL Pro
SY100EP196V
Micrel, Inc.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
For best performance, use good high frequency layout
techniques, filter V
CC
supplies, and keep ground connections
short. Use multiple vias where possible. Also, use controlled
impedance transmission lines to interface with the
SY100EP196V data inputs and outputs.
V
BB
Supply
The VBB pin is an internally generated supply, and is
available for use only by the SY100EP196V. When unused,
this pin should be left unconnected. The two common uses
for V
BB
are to handle a single-ended PECL input, and to re-
bias inputs for AC-coupling applications.
If IN, /IN is driven by a single-ended output, V
BB
is used
to bias the unused input. Please refer to Figures 9. The
PECL signal driving SY100EP196V may optionally be
inverted in this case.
When the signal is AC-coupled, V
BB
is used, as shown
in Figure 10, to re-bias IN, /IN. This ensures that
SY100EP196V inputs are within its acceptable common
mode range.
In all cases, V
BB
current sinking or sourcing must be
limited to 0.5mA or less.
APPLICATIONS INFORMATION
Setting D Input Logic Thresholds
As explained earlier, in all designs where the
SY100EP196V V
EE
supply is at zero volts, the D inputs
may accommodate CMOS and TTL level signals, as well as
PECL or LVPECL. Figures 9 show how to connect V
CF
and
V
EF
for all possible cases.
Cascading
Two or more SY100EP196V may be cascaded, in order
to extend the range of delays permitted. Each additional
SY100EP196V adds about 2200ps to the minimum delay,
and adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY100EP196V. Using this internal circuitry, SY100EP196V
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY100EP196V appear
in Figures 10. Table 7 lists the nominal delay for all the
cases that appear in Figures 10.
IN
/IN
Q
/Q
IN
/IN
Q
FTUNE
FTUNE
/Q
D[9:0]
SY100EP196V
SY100EP196V
D[10]
#2
#1
SETMIN
SETMAX
/CASCADE
CASCADE
C[9:0]
C[10]
Control Word (11bits)
DAC
Figure 10a. Cascading Two SY100EP196V
IN
/IN
Q
/Q
IN
/IN
Q
/Q
SY100EP196V
SY100EP196V
D[10]
#3
DAC
#2
SETMIN
SETMAX
SETMIN
SETMAX
/CASCADE
CASCADE
C[11]
IN
/IN
/CASCADE
Q
FTUNE
FTUNE
/Q
D[9:0]
SY100EP196V
D[10]
#1
CASCADE
C[9:0]
C[10]
Control Word (12bits)
Figure 10b. Cascading Three SY100EP196V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100EP196VTG TR | 功能描述:延遲線/計時元素 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100EP196VTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:100EP, ECL Pro® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP196VTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:100EP, ECL Pro® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100EP210UTG | 功能描述:緩沖器和線路驅(qū)動器 2.5-5V Dual 1:5 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| SY100EP210UTG TR | 功能描述:緩沖器和線路驅(qū)動器 2.5-5V Dual 1:5 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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