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參數(shù)資料
| 型號： | SY10E016JY TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UPCOUNTER 8BIT SYNC 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 10E |
| 邏輯類型： | 二進(jìn)制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 復(fù)位： | 異步 |
| 計時： | 同步 |
| 計數(shù)速率： | 900MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY10E016JYTR SY10E016JYTR-ND |
8
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
is used as the divide output and the pulse duration is equal to
a full clock period. For even divide ratios twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip-flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2 to
256, inclusive. If divide ratios of greater than 256 are needed,
multiple E016s can be cascaded in a manner similar to that
already discussed. When E016s are cascaded to build larger
dividers, the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters until all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
Figure 4 on the following page shows a typical block
diagram of a 32-bit divider chain. Once again, the maximize
the frequency of operation, E101 OR gates were used. For
lower frequency applications, a slower OR gate could replace
the E101. Note that for a 16-bit divider, the OR function
feeding the PE (program enable) input CANNOT be replaced
by a wire OR tie as the TC output of the least significant E016
must also feed the CE input of the most significant E016. If the
two TC outputs were OR tied, the cascaded count operation
would not operate properly. Because in the cascaded form
the PE feedback is external and requires external gating, the
maximum frequency of operation will be significantly less than
the same operation in a single device.
Maximizing E016 Count Frequency
The E016 device produces nine fast transitioning single-
ended outputs; thus, VCC noise can become significant in
situations where all of the outputs switch simultaneously in the
same direction. This VCC noise can negatively impact the
maximum frequency of operation of the device. Since the
device does not need to have the Q outputs terminated to
count properly, it is recommended that, if the outputs are not
going to be used in the rest of the system, they should be left
unterminated. In addition, if only a subset of the Q outputs are
used in the system, only those outputs should be terminated.
Not terminating the unused outputs will not only cut down the
VCC noise generated, but will also save in total system power
dissipation. Following these guidelines will allow designers to
either be more aggressive in their designs, or provide them
Divide
Preset Data Inputs
Ratio
P7
P6
P5
P4
P3
P2
P1
P0
2
H
HHH
L
3
H
HHH
H
L
H
4
H
HHH
H
L
5
H
HHH
L
H
112
H
L
H
L
113
H
L
H
114
H
L
H
L
254
L
H
L
255
L
H
256
L
Table 1. Preset Values for Various Divide Ratios
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