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參數(shù)資料
| 型號(hào)： | SY10E136JCTR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | RECTIFIER STANDARD SINGLE 3A 800V 800 200A-ifsm 10uA-ir 1V-vf DO-201AD 1.2K/REEL-13 |
| 中文描述： | 10E SERIES, SYN POSITIVE EDGE TRIGGERED 6-BIT BIDIRECTIONAL BINARY COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 119K |
| 代理商： | SY10E136JCTR |
6
SY10E136
SY100E136
Micrel
count status for the next occurrence of terminal count on
the LSC. This ripple propagation will not affect the count
frequency as it has 2
6
-1 or 63 clock pulses to ripple through
without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the set-up time of the CL
IN
input. This limit
will consist of the CLK to CL
OUT
delay of the E136, plus the
CL
IN
set-up time, plus any path length differences between
the CL
OUT
output and the clock.
Programmable Divider
Using external feedback of the C
OUT
pin, the E136 can
be configured as a programmable divider. Figure 3 illustrates
the configuration for a 6-bit count-down programmable
divider. If for some reason a count-up divider is preferred,
the C
OUT
signal is simply fed back to S
2
rather than S
1
.
Examination of the truth table for the E136 shows that when
both S
1
and S
2
are LOW, the counter will parallel load on
the next positive transition of the clock. If the S
2
input is
low and the S
1
input is high, the counter will be in the
count-down mode and will count towards an all zero state
upon successive clock pulses. Knowing this and the
operation of the C
OUT
output, it becomes a trivial matter to
build programmable dividers.
For a programmable divider, one must to load a
predesignated number into the counter and count to terminal
count. Upon terminal count, the counter should automatically
reload the divide number. With the architecture shown in
Figure 3, when the counter reaches terminal count, the
C
OUT
output, and thus the S
1
input, will go LOW. This,
combined with the low on S
2
will cause the counter to load
the inputs present on D
0
–
D
5
. Upon loading the divide value
into the counter, C
OUT
will go HIGH as the counter is no
longer at terminal count, thereby placing the counter back
into the count mode.
CLK
C
IN
CL
IN
ACTIVE
LOW
D
Q
Figure 2. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry output
(CL
OUT
) pulses low one clock pulse before the counter
reaches terminal count. Also note that both CL
OUT
and the
carry-out pin (C
OUT
) of the device pulse low for only one
clock period. The input structure for look-ahead-carry-in
(CL
IN
) and carry-in (C
IN
) is pictured in Figure 2.
The CL
IN
input is registered and then OR'ed with the C
IN
input. From the truth table one can see that both the C
IN
and the CL
IN
inputs must be in a LOW state for the E136 to
be enabled to count (either count up or count down). The
CL
IN
inputs are driven by the CL
OUT
output of the lower
order E136 and, therefore, are only asserted for a single
clock period. Since the CL
IN
input is registered, it must be
asserted one clock period prior to the C
IN
input.
If the counter previous to a given counter is at terminal
count, its C
OUT
output, and thus the C
IN
input of the given
counter will be in the "LOW" state. This signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CL
OUT
output of the LSC will pulse low one clock period before it
reaches terminal count. This CL
OUT
signal will be clocked
into the CL
IN
input of the higher order counters on the
following positive clock transition. Since both C
IN
and CL
IN
are in the LOW state, the next clock pulse will cause the
least significant counter to roll over and all higher order
counters, if signaled by the C
IN
inputs, to count by one.
During the clock pulse in which the higher order counter
is counting by one, the CL
IN
is clocking in the high signal
presented by the CL
OUT
of the LSC. The C
IN
s in the higher
order counter will ripple through the chain to update the
CLK
CLOCK
C
OUT
Q
0
–
Q
5
D
0
–
D
5
S
0
S
1
"LO"
C
OUT
Figure 3. 6-bit Programmable Divider
Divide
Ratio
Preset Data Inputs
D3
D5
D4
D2
D1
D0
2
3
4
5
*
*
L
L
L
L
*
*
H
H
H
*
*
H
H
H
L
L
L
L
*
*
L
L
L
*
*
H
H
H
L
L
L
L
*
*
L
L
L
*
*
H
H
H
L
L
L
H
*
*
L
H
H
*
*
H
H
H
L
H
H
L
*
*
H
L
L
*
*
L
H
H
H
L
H
L
*
*
H
L
H
*
*
H
L
H
36
37
38
*
*
62
63
64
Table 1. Preset Inputs Versus Divide Ratio
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| SY10E136JZ | 功能描述:計(jì)數(shù)器移位寄存器 6-bit Universal Up/Down Counter (Lead Free) RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| SY10E136JZ TR | 功能描述:計(jì)數(shù)器移位寄存器 6-bit Universal Up/Down Counter (Lead Free) RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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