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參數(shù)資料
| 型號(hào)： | SY10E137JZ TR |
| 廠(chǎng)商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER RIPPLE 8BIT 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 10E |
| 邏輯類(lèi)型： | 二進(jìn)制計(jì)數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 復(fù)位： | 異步 |
| 計(jì)時(shí)： | 異步/同步 |
| 計(jì)數(shù)速率： | 2.2GHz |
| 觸發(fā)器類(lèi)型： | 正邊沿 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線(xiàn)） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | SY10E137JZTR SY10E137JZTR-ND |
1
SY10E137
SY100E137
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
CLK, CLK
Differential Clock Inputs
Q0–Q7, Q0–Q7
Differential Q Outputs
A_Start
Asynchronous Enable Input
EN1, EN2
Synchronous Enable Inputs
MR
Asynchronous Master Reset
VBB
Switching Reference Output
VCCO
VCC to Output
FEATURES
s 1.8GHz min. count frequency
s Extended 100E VEE range of –4.2V to –5.5V
s Synchronous and asynchronous enable pins
s Differential clock input and data output pins
s VBB output for single-ended use
s Asynchronous Master Reset
s Internal 75K
input pull-down resistors
s Available in 28-pin PLCC packge
DESCRIPTION
The SY10/100E137 are very high speed binary ripple
counters. The two least significant bits were designed
with very fast edge rates, while the more significant bits
maintain standard ECLinPS output edge rates. This allows
the counters to operate at very high frequencies, while
maintaining a moderate power dissipation level.
The devices are ideally suited for multiple frequency
clock generation, as well as for counters in high-
performance ATE time measurement boards.
Both asynchronous and synchronous enables are
available to maximize the device's flexibility for various
applications. The asynchronous enable input, A_Start,
when asserted, enables the counter while overriding any
synchronous enable signals. The E137 features XOR'ed
enable inputs, EN1 and EN2, which are synchronous to
the CLK input. When only one synchronous enable is
asserted, the counter becomes disabled on the next CLK
transition. All outputs remain in the previous state poised
for the other synchronous enable or A_Start to be
asserted in order to re-enable the counter.
Asserting
both synchronous enables causes the counter to become
enabled on the next transition of the CLK. EN1 (or EN2)
and CLK edges are coincident. Sufficient delay has been
inserted in the CLK path (to compensate for the XOR
gate delay and the internal D-flip-flop set-up time) to
ensure that the synchronous enable signal is clocked
correctly; hence, the counter is disabled.
The E137 can also be driven single-endedly utilizing
the VBB output supply as the voltage reference for the
CLK input signal. If a single-ended signal is to be used,
the VBB pin should be connected to the CLK input and
bypassed to ground via a 0.01
F capacitor. VBB can
only source/sink 0.5mA; therefore, it should be used as
a switching reference for the E137 only.
All input pins left open will be pulled LOW via an input
pull-down resistor. Therefore, do not leave the differential
CLK inputs open. Doing so causes the current source
transistor of the input clock gate to become saturated,
thus upsetting the internal bias regulators and
jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to
an all zero state upon assertion.
PIN NAMES
8-BIT RIPPLE
COUNTER
SY10E137
SY100E137
Rev.: E
Amendment: /0
Issue Date: March 2006
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