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參數(shù)資料
| 型號(hào)： | SY58024UMG TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH DUAL 32MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 2 x 2:2 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.375 V ~ 2.625 V |
| 電流 - 電源： | 200mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY58024UMGTR SY58024UMGTR-ND |
5
Precision Edge
SY58024U
Micrel, Inc.
M9999-082807
hbwhelp@micrel.com or (408) 955-1690
VCC = +2.5V ±5% or +3.3V ±10%; RL = 100 across each output pair; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
V
IN ≥ 100mV; VOUT ≥ 200mV
Clock
6
GHz
NRZ Data
10.7
Gbps
tpd
Propagation Delay
IN-to-Q
200
350
ps
SEL-to-Q
100
400
ps
tSKEW
Channel-to-Channel Skew
(Within Bank)
Note 8
20
ps
Part-to-Part Skew
Note 9
75
ps
tJITTER
Clock
Cycle-to-Cycle Jitter
Note 10
1psRMS
Total Jitter
Note 11
10
psPP
Data
Random Jitter
Note 12
1psRMS
Deterministic Jitter
Note 13
10
psPP
Crosstalk Induced Jitter
Note 14
0.7
psRMS
Adjacent Channel
tr, tf
Output Rise/Fall Time
20% to 80% at full swing.
25
60
ps
Notes:
7.
High frequency AC-parameters are guaranteed by design and characterization.
8.
Skew is measured between outputs of the same bank under identical transitions.
9.
Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
10. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n–Tn–1 where T is the time between rising edges of the output
signal.
11. Total jitter definition: With an ideal clock input of frequency ≤ fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
12. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps–3.2Gbps.
13. Deterministic jitter is measured at 2.5Gbps–3.2Gbps with both K28.5 and 223–1 PRBS pattern.
14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while
applying similar, differential clock frequencies that are asynchronous with respect to each other at inputs.
AC ELECTRICAL CHARACTERISTICS(7)
V
CC = +3.3V ±10% or +2.5V ±5%; RL = 100 across each pair; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output HIGH Voltage
Q0, /Q0; Q1, /Q1
V
CC–0.020
V
CC
V
OUT
Output Voltage Swing
Q0, /Q0; Q1, /Q1; see Figure 1a.
325
400
500
mV
V
DIFF_OUT
Differential Voltage Swing
Q0, /Q0; Q1, /Q1; see Figure 1b.
650
800
1000
mV
R
OUT
Output Source Impedance
Q0, /Q0; Q1, /Q1
40
50
60
Notes:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
CML OUTPUT DC ELECTRICAL CHARACTERISTICS(6)
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參數(shù)描述 |
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| SY58024UMI | 功能描述:IC CROSSPOINT SWITCH DUAL 32MLF RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:48 系列:- 功能:開關(guān) 電路:4 x SPST - NO 導(dǎo)通狀態(tài)電阻:100 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| SY58024UMI TR | 功能描述:IC CROSSPOINT SWITCH DUAL 32MLF RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:48 系列:- 功能:開關(guān) 電路:4 x SPST - NO 導(dǎo)通狀態(tài)電阻:100 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| SY58024UMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:CROSSPOINT SWITCH CML OUTPUTS AND INTERNAL I/O TERMINATION |
| SY58024UMY | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:CROSSPOINT SWITCH CML OUTPUTS AND INTERNAL I/O TERMINATION |
| SY58024UMYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:CROSSPOINT SWITCH CML OUTPUTS AND INTERNAL I/O TERMINATION |
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