Precision Edge SY58025U Micrel, Inc. M9999-082707 hbwhelp@micrel.com or (408) 955-1690 PACKAGE/ORDERI" />
參數(shù)資料
型號: SY58025UMG
廠商: Micrel Inc
文件頁數(shù): 4/11頁
文件大小: 0K
描述: IC MUX DUAL 2:1 DIFF CML 32MLF
標(biāo)準(zhǔn)包裝: 60
系列: SY58
類型: 多路復(fù)用器
電路: 1 x 2:1
獨(dú)立電路: 2
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1382
2
Precision Edge
SY58025U
Micrel, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Pin Number
Pin Name
Pin Function
25, 28,
INA0, /INA0,
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
29, 32,
INA1, /INA1,
accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair
1, 4,
INB0, /INB0,
internally terminates to a VT pin through 50. Note that these inputs will default to an
5, 8
INB1, /INB1
indeterminate state if left open. Unused differential input pairs can be terminated by
connecting one input to VCC and the complementary input to GND through a 1k resistor.
The VT pin is to be left open in this configuration. Please refer to the “Input Interface
Applications” section for more details.
26, 30, 2, 6
VTA0 , VTA1,
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT
VTB0, VTB1
pin. Each VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “Input Interface Applications” section for more details.
18, 15
SELA, SELB
Bank A, Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs
select the inputs to the multiplexers. These inputs are internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold
is VCC/2.
27, 31, 3, 7
VREF-ACA0,
Reference Output Voltage: These outputs bias to VCC –1.2V. Connect to the VT pin when
VREF-ACA1,
AC-coupling the data inputs. Bypass with 0.01F low ESR capacitor to VCC. Maximum
VREF-ACB0,
current source or sink is 0.5mA. See “Input Interface Applications” section.
VREF-ACB1
10, 13, 16,
VCC
Positive Power Supply: Bypass with 0.1F
0.01F low ESR capacitors.
17, 20, 23
22, 21,
QA, /QA,
Differential CML Outputs: MUX A and MUX B selected CML outputs. See “Output
12, 11
QB, /QB
Interface Applications” section for termination. Refer to the “Truth Table” for logic
operation.
9, 24
GND,
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Exposed pad
14, 19
NC
Not connected.
PIN DESCRIPTION
24
23
22
21
20
19
18
17
GND
VCC
QA
/QA
VCC
NC
SELA
VCC
INB0
VTB0
VREF-ACB0
/INB0
INB1
VTB1
VREF-ACB1
/INB1
1
2
3
4
5
6
7
8
910 11 12 13 14 15 16
32 31 30 29 28 27 26 25
/INA0
INA1
VTA1
VREF-ACA1
INA1
VREF-ACA0
VTA0
INA0
VCC
QB
/QB
VCC
GND
NC
SELB
VCC
32-Pin MLF (MLF-32)
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY58025UMI
MLF-32
Industrial
SY58025U
Sn-Pb
SY58025UMITR(2)
MLF-32
Industrial
SY58025U
Sn-Pb
SY58025UMG(3)
MLF-32
Industrial
SY58025Uwith
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY58025UMGTR(2, 3)
MLF-32
Industrial
SY58025U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
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