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參數(shù)資料
| 型號(hào)： | SY58026UMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX DUAL 2:1 DFF LVPECL 32MLF |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | SY58 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 2:1 |
| 獨(dú)立電路： | 2 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1089 (CN2011-ZH PDF) |
| 其它名稱： | 576-1383 |
5
Precision Edge
SY58026U
Micrel, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 50 to VCC–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
NRZ Data
5
Gbps
VOUT 400mV
Clock
6
GHz
tpd
Propagation Delay
IN-to-Q
VIN 300mV
160
230
310
ps
SEL-to-Q
100
220
400
ps
tSKEW
Input-to-Input Skew (Within-bank)
Note 8
715
ps
Bank-to-Bank Skew
Note 9
820
ps
Part-to-Part Skew
Note 10
100
ps
tJITTER
Data
Random Jitter (RJ)
Note 11
1psRMS
Deterministic Jitter (DJ)
Note 12
10
psPP
Clock
Cycle-to-Cycle Jitter (RJ)
Note 13
1psRMS
Total Jitter (TJ)
Note 14
10
psPP
Crosstalk-induced Jitter
Channel-to-Channel (Within-bank)
Note 15, Within-bank.
0.7
psRMS
tr, tf
Output Rise/Fall Time 20% to 80%
At full swing.
35
70
110
ps
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. VIN swing 100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 223–1 PRBS pattern
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency - fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
AC ELECTRICAL CHARACTERISTICS(7)
TRUTH TABLES
INA0
/INA0
INA1
/INA1
SELA
QA
/QA
01
X
0
1
10
X
0
1
0
XX
0
1
0
1
XX
1
0
1
0
INB0
/INB0
INB1
/INB1
SELB
QB
/QB
01
X
0
1
10
X
0
1
0
XX
0
1
0
1
XX
1
0
1
0
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| SY58026UMG TR | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 10.7Gbps Dual 2:1 800mV LVPECL Multiplexer (I Temp, Green) RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY58026UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ULTRA PRECISION DUAL 2:1 LVPECL MUX WITH INTERNAL TERMINATION |
| SY58026UMI | 功能描述:IC MUX DUAL 2:1 DFF LVPECL 32MLF RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器 系列:SY58 標(biāo)準(zhǔn)包裝:25 系列:74HC 類型:解碼器 電路:1 x 2:4 獨(dú)立電路:2 輸出電流高，低:5.2mA，5.2mA 電壓電源:單電源 電源電壓:2 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-DIP 包裝:管件 |
| SY58026UMI TR | 功能描述:IC MUX 10.7GBPS DUAL 2:1 32-MLF RoHS:否 類別:集成電路 (IC) >> 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器 系列:SY58 標(biāo)準(zhǔn)包裝:25 系列:74HC 類型:解碼器 電路:1 x 2:4 獨(dú)立電路:2 輸出電流高，低:5.2mA，5.2mA 電壓電源:單電源 電源電壓:2 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-DIP 包裝:管件 |
| SY58026UMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ULTRA PRECISION DUAL 2:1 LVPECL MUX WITH INTERNAL TERMINATION |
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