參數(shù)資料
型號: SY58027UMITR
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: ULTRA PRECISION DUAL 2:1 400mV LVPECL MUX WITH INTERNAL TERMINATION
中文描述: 58027 SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, QCC32
封裝: 5 X 5 MM, MLF-32
文件頁數(shù): 5/10頁
文件大?。?/td> 172K
代理商: SY58027UMITR
5
Precision Edge
SY58027U
Micrel, Inc.
M9999-020207
hbwhelp@micrel.com or (408) 955-1690
TRUTH TABLES
INA0
0
1
X
X
/INA0
1
0
X
X
INA1
X
X
0
1
/INA1
X
X
1
0
SELA
0
0
1
1
QA
0
1
0
1
/QA
1
0
1
0
INB0
0
1
X
X
/INB0
1
0
X
X
INB1
X
X
0
1
/INB1
X
X
1
0
SELB
0
0
1
1
QB
0
1
0
1
/QB
1
0
1
0
AC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V
±
5% or 3.3V
±
10%; T
A
=
40
°
C to +85
°
C; R
L
= 50
to V
CC
2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
NRZ Data
Clock
10.7
Gbps
GHz
V
OUT
200mV
7
t
pd
Propagation Delay
IN-to-Q
V
IN
300mV
140
215
290
ps
SEL-to-Q
100
220
400
ps
t
SKEW
Input-to-Input Skew (Within-bank)
Note 8
6
15
ps
Bank-to-Bank Skew
Note 9
8
20
ps
Part-to-Part Skew
Note 10
100
ps
t
JITTER
Data
Random Jitter (RJ)
Note 11
1
ps
RMS
ps
PP
ps
RMS
ps
PP
Deterministic Jitter (DJ)
Note 12
10
Clock
Cycle-to-Cycle Jitter (RJ)
Note 13
1
Total Jitter (TJ)
Note 14
10
Crosstalk-Induced Jitter
Channel-to-Channel
Note 15,
Within-bank.
0.7
ps
RMS
ps
t
r
, t
f
Output Rise/Fall Time 20% to 80%
At full swing.
20
55
80
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. V
IN
swing
100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2
23
1 PRBS pattern.
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
T
n
1
where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
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