參數(shù)資料
型號： SY58030UMYTR
廠商： MICREL INC
元件分類： 編、解碼器及復(fù)用、解復(fù)用
英文描述： 58030 SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, QCC44
封裝： 7 X 7 MM, LEAD FREE, MO-220, MLF-44
文件頁數(shù)： 5/11頁
文件大小： 202K
代理商： SY58030UMYTR
3
Precision Edge
SY58037U
Micrel
PACKAGE/ORDERING INFORMATION
Pin Number
Pin Name
Pin Function
20, 18,
IN0, /IN0,
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept
16, 14,
IN1, /IN1,
AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT
13, 11,
IN2, /IN2,
pin through 50
. Note that these inputs will default to an indeterminate state if left open.
9, 7,
IN3, /IN3,
Please refer to the “Input Interface Applications” section for more details.
5, 3,
IN4, /IN4,
1, 43,
IN5,/IN5,
42, 40,
IN6, /IN6,
38, 36
IN7, /IN7
19,15,
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin.
12, 8,
VT2, VT3,
The VT pins provide a center-tap to a termination network for maximum interface flexibility.
4, 44,
VT4, VT5,
See “Input Interface Applications” section for more details.
41, 37
VT6, VT7
17,
VREF-AC0,
Reference Voltage: This output biases to V
CC–1.2V. It is used when AC coupling the inputs
10,
VREF-AC1,
(IN, /IN). For AC-coupled applications, connect VREF_AC to the VT pin and bypass with a
2
VREF-AC2,
0.01
F low ESR capacitor to V
CC. See “Input Interface Applications” section for more details.
39
VREF-AC3
21,
SEL0,
The TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that this input is
22,
SEL1,
internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open.
35
SEL2
24, 27, 29, 32
VCC
Positive Power Supply. Bypass with 0.1
F0.01F low ESR capacitors as close to each VCC
pin.
25, 26,
Q0,/Q0,
Differential Outputs: These CML output pairs are the outputs of the device. Please refer to
30, 31
Q1,/Q1
the truth table below for details. Unused output pairs may be left open. Each output is designed
to drive 400mV into 100
across each output pair.
23, 28, 33
GND,
Ground. GND and exposed pad must both be connected to the most negative potential of chip
Exposed Pad
ground.
PIN DESCRIPTION
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
12 13 14 15 16 17 18 19
44 43 42 41 40 39 38 37
IN5
VREF-AC2
/IN4
VT4
IN4
NC
/IN3
VT3
GND
VCC
/Q1
Q1
VCC
GND
VCC
/Q0
/IN6
VT6
IN6
/IN5
VT5
VREF-AC3 IN7 VT7
9
10
11
25
24
23
20 21 22
35
IN3
VREF-AC1
/IN2
Q0
VCC
GND
36
34
NV
SEL2
/IN7
IN1
VT1
/IN1
IN2
VT2
VREF-AC0
/IN0
VT0
SEL1
SEL0
IN0
44-Pin MLF (MLF-44)
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY58037UMI
MLF-44
Industrial
SY58037U
Sn-Pb
SY58037UMITR(2)
MLF-44
Industrial
SY58037U
Sn-Pb
SY58037UMY(3)
MLF-44
Industrial
SY58037U with
Pb-Free
Pb-Free bar-line indicator
Matte-Sn
SY58037UMYTR(2, 3)
MLF-44
Industrial
SY58037U with
Pb-Free
Pb-Free bar-line indicator
Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
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