參數(shù)資料
型號: SY58608U
廠商: Micrel Semiconductor,Inc.
英文描述: 3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input
中文描述: 3.2Gbps速率精密,1:2 LVDS扇出緩沖器,內(nèi)部終止和故障安全輸入
文件頁數(shù): 5/12頁
文件大小: 286K
代理商: SY58608U
Micrel, Inc.
SY58608U
October 2006
5
M9999-102706-A
hbwhelp@micrel.com
or (408) 955-1690
AC Electrical Characteristics
(8)
V
CC
= +2.5V ±5%, R
L
= 100
across the output pairs, Input t
r
/t
f
:
300ps; T
A
= –40°C to +85°C,
unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
4.25
Gbps
f
MAX
Maximum Frequency
V
OUT
> 200mV Clock
2
3
GHz
V
IN
: 100mV-200mV
170
280
420
ps
t
PD
Propagation Delay IN-to-Q
V
IN
: 200mV-800mV
130
200
300
ps
Within Device Skew
Note 9
5
20
ps
t
Skew
Part-to-Part Skew
Note 10
135
ps
Data Random Jitter
Note 11
1
ps
RMS
ps
PP
Deterministic Jitter
Note 12
10
Clock Cycle-to-Cycle Jitter
Note 13
1
ps
RMS
t
Jitter
Total Jitter
Note 14
10
ps
PP
t
r,
t
f
Output Rise/Fall Time
(20% to 80%)
At full output swing.
35
60
100
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
8.
9.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 pattern, measured at
f
MAX
.
12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23
–1 PRBS pattern.
13. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t
JITTER
_
CC
= T
n
–T
n+1
,
where T is the time between rising edges of the output signal.
14. Total jitter definition: with an ideal clock input frequency of
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by
more than the specified peak-to-peak jitter value.
These high-speed parameters are Guaranteed by design and characterization.
Within-device skew is measured between two different outputs under identical input transitions.
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