V
參數(shù)資料
型號(hào): SY58609UMG
廠商: Micrel Inc
文件頁數(shù): 10/14頁
文件大?。?/td> 0K
描述: IC MUX 2:1 CML FSI INPUT 16-MLF
標(biāo)準(zhǔn)包裝: 100
系列: SY58
類型: 多路復(fù)用器
電路: 2 x 2:1
獨(dú)立電路: 1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-2051-5
SY58609UMG-ND
Micrel, Inc.
SY58609U
August 2007
5
M9999-082907-C
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
(8)
VCC = +2.5V ±5% or +3.3V ±10%, RL = 100
across the outputs; Input t
R/tF < 300ps, TA = –40°C to +85°C, unless
otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Frequency
NRZ Data
4.25
Gbps
VOUT > 200mV
Clock
2.5
3
GHz
tPD
Propagation Delay
IN-to-Q
VIN: 100mV-200mV
180
330
450
ps
VIN: >200mV
140
270
370
ps
SEL-to-Q
150
450
ps
tSkew
Input-to-Input Skew
Note 9, 10
5
20
ps
Part-to-Part Skew
Note 11
150
ps
tJitter
Data
Random Jitter
Note 12
1
psRMS
Deterministic Jitter
Note 13
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 14
1
psRMS
Total Jitter
Note 15
10
psPP
tR,tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
35
50
90
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
8.
High-frequency AC-parameters are guaranteed by design and characterization.
9.
Input-to-Input skew is the time difference between the two inputs and one output, under identical input transitions.
9.
Input-to-Input Skew is included in IN-to-Q propagation delay.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at
the edges at the respective inputs.
12. Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX.
13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
15. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX (device), no more than one output edge in 10^12 output edges will deviate by
more than the specified peak-to-peak jitter value.
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