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參數(shù)資料
| 型號(hào)： | SY69952 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | Raised Panel Label; External Height:0.49"; External Width:1.06"; Label Material:Polyester; Color:Yellow; Features:Foam-Backed Raised Design; Permanent Acrylic Adhesive; Thermal Transfer Print Quality RoHS Compliant: Yes |
| 中文描述： | OC-3/STS-3鐘回收收發(fā)器 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | SY69952 |
DESCRIPTION
FEATURES
SY69952
Rev.: M
Issue Date:
Amendment: /0
October, 1998
I
A complete ATM compatible single chip Transmitter
and Receiver
I
Seamless operation with PMC-Sierra PM5345, VLSI
VNS67200, Ig
T WAC-013-B/WAC-413-A and
NEC
μ
PD98402 UNI Processors
I
Supports clock and data recovery from 51.84 Mbit/s
or 155.52 Mbit/s NRZ or NRZI data stream
I
155.52MHz clock multiplication from 19.44MHz
source or 51.84MHz clock multiplication from
6.48MHz source
I
Line Receiver Inputs: No external buffering needed
I
Differential output buffering
I
Link Status Indication
I
Loop-back testing
I
100K ECL compatible I/O
I
Single +5 volt power supply
I
Replacement for Cypress CY7B952
I
The SY69952 complies with Bellcore, ITU/CCITT &
ANSI specifications
I
Available in 28-pin SOIC package
Micrel-Synergy's SY69952 contains fully integrated
transmitter and receiver functions designed to provide
clock recovery and generation for either 51.84Mbit/s OC/
STS-1 or 155.52Mbit/s OC/STS-3 SONET/SDH
(SY69952) and ATM applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL) allowing use of 19.44MHz
reference for 155.52MHz generation or a 6.48MHz
reference for 51.84MHz generation. Clock recovery is
performed by synchronizing the on-chip VCO directly to
the incoming data stream.
The SY69952 meets the jitter compliance criteria of
Bellcore, ITU/CCITT and ANSI standards. Low jitter is
ensured by Micrel-Synergy's advanced PLL technology
and positive ECL (PECL) I/O.
Micrel-Synergy's circuit design techniques coupled with
ASSET bipolar technology result in ultra-fast
performance with low noise and low power dissipation.
OC-3/STS-3
CLOCK RECOVERING
TRANSCEIVER
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ROUT+
ROUT-
RIN+
RIN-
MODE
V
CC
CD
LOOP
REFCLK-
REFCLK+
TOUT-
TOUT+
PLL1+
PLL1-
PLL2-
PLL2+
TSER-
TSER+
TCLK+
TCLK-
V
CC
V
EE
V
CC
LFI
RSER+
RSER-
RCLK+
RCLK-
PLL
PLL
x8
RECEIVE
TRANSMIT
REFCLK+
REFCLK-
PLL1+
PLL1-
ROUT+
ROUT-
RIN+
RIN-
TOUT+
TOUT-
RCLK+
RCLK-
RSER+
RSER-
TSER+
TSER-
TCLK+
TCLK-
MODE
PLL2+
PLL2-
LOOP
LFI
CD
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY69952_05 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER |
| SY69952_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER |
| SY69952A | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER |
| SY69952AZC | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ATM/SONET TRANSCEIVER|SOP|28PIN|PLASTIC |
| SY69952ZC | 功能描述:IC TXRX CLOCK RECOVERY 28-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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