參數(shù)資料
型號(hào): SY87700LZI
英文描述: High Efficient Rectifier Diodes
中文描述: 時(shí)鐘/數(shù)據(jù)恢復(fù)|雙極|專(zhuān)科| 28腳|塑料
文件頁(yè)數(shù): 14/14頁(yè)
文件大?。?/td> 168K
代理商: SY87700LZI
SY87700L
14
Micrel
MICREL-SYNERGY
3250 SCOTT BOULEVARD
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
2002 Micrel Incorporated
SANTA CLARA
CA 95054
USA
APPENDIX A
Layout and General Suggestions
1.
2.
3.
4.
Establish controlled impedance stripline, microstrip, or co-planar construction techniques.
Signal paths should have, approximately, the same width as the device pads.
All differential paths are critical timing paths, where skew should be matched to within
±
10ps.
Signal trace impedance should not vary more than
±
5%. If in doubt, perform TDR analysis of all high-speed signal
traces.
Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to
reduce stray capacitance. Be careful of crosstalk coupling into the filter network.
Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals.
Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based
oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter.
Evaluate ASIC AND FPGA REFIN source clocks with suitable jitter analysis equipment, such as TDS11801 tektronix
DSO oscilloscope, or Wavecrest DTS2077 Time Interval Analyzer.
All unused outputs require termination.
5.
6.
7.
8.
9.
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