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參數(shù)資料
| 型號(hào)： | SY87701ALZI |
| 廠商： | MICREL INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大小： | 168K |
| 代理商： | SY87701ALZI |
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SY87701AL
4
Micrel, Inc.
M9999-111506
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, then PLL will be
declared out of lock, and the PLL will lock to the reference
clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30
μ
s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY87701AL contains a link fault indication circuit
that monitors the integrity of the serial data input. If the
recovered serial data from RDIN is at the correct data rate
(within 1000ppm of the synthesizer frequency), the Link
Fault Indicator (LFIN) output will be asserted HIGH indicating
an in-lock condition and will remain HIGH as long as this
condition is met.
In the event that the recovered serial data is not at the
correct data rate (greater than 1000ppm difference from the
synthesizer frequency), then LFIN output will go LOW
indicating an out-of-lock condition. This condition will force
the Clock and Data Recovery PLL (CDR) to lock onto the
synthesizer frequency until it is within the correct frequency
range (less than 1000ppm difference from the synthesizer
frequency). Once the CDR is within the correct frequency
range it will again lock onto the RDIN input.
During the interval when the CDR is not locked onto the
RDIN input, the LFIN output will not be a static LOW, but
will be changing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY87701ALHG | 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| SY87701ALHI | 3.3V 28Mbps to 1.3Gbps AnyRate Clock and Data Recovery |
| SY87701LHG | 3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87701LHGTR | 3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87701LHITR | 3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87701L | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87701AL for new designs |
| SY87701L_06 | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY |
| SY87701L_11 | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87701AL for new designs |
| SY87701LGI | 制造商:Micrel Inc 功能描述: |
| SY87701LHG | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 3.3V Any-Rate 32-1250 Mbps CDR (I Temp, Green/32 Pin EP-TQFP/Bulk) RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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