參數(shù)資料
型號: SY87701LHI
廠商: Micrel Inc
文件頁數(shù): 9/14頁
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY 32-TQFP
標(biāo)準(zhǔn)包裝: 250
系列: AnyRate®
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,ATM 應(yīng)用
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.25Gbps
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-EPAD-TQFP
包裝: 托盤
SY87701L
4
Micrel, Inc.
M9999-111506
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram generates
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY87701L contains a link fault indication circuit which
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will poll the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
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