參數(shù)資料
型號(hào): SY87701VZC
廠商: MICREL INC
元件分類: 數(shù)字傳輸電路
英文描述: 5V/3.3V 32-1250Mbps AnyRate⑩ CLOCK AND DATA RECOVERY
中文描述: CLOCK RECOVERY CIRCUIT, PDSO28
封裝: 0.300 INCH, SOIC-28
文件頁數(shù): 3/12頁
文件大小: 152K
代理商: SY87701VZC
SY87701V
3
Micrel
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram generates
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30
μ
s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY87701V contains a link fault indication circuit which
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will pull the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
RDOUTP, RDOUTN [Receive Data Output]
Differential
PECL.
These ECL 100K outputs (+3.3V or +5V referenced)
represent the recovered data from the input data stream
(RDIN). This recovered data is sampled on the rising edge
of RCLK.
RCLKP, RCLKN [Clock Output]
Differential PECL.
These ECL 100K outputs (+3.3V or +5V referenced)
represent the recovered clock used to sample the recovered
data (RDOUT).
TCLKP, TCLKN [Clock Output]
Differential PECL.
These ECL 100K outputs (+3.3V or +5V referenced)
represent either the recovered clock (CLKSEL = HIGH) used
to sample the recovered data (RDOUT) or the transmit clock
of the frequency synthesizer (CLKSEL = LOW).
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
External loop filter pins for the clock synthesis PLL.
PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
External loop filter pins for the receiver PLL.
POWER & GROUND
V
CC
V
CCA
V
CCO
GND
N/C
Supply Voltage
(1)
Analog Supply Voltage
(1)
Output Supply Voltage
(1)
Ground
No Connect
NOTE:
1. V
CC
, V
CCA
, V
CCO
must be the same value.
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相關(guān)代理商/技術(shù)參數(shù)
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SY87701VZH TR 功能描述:計(jì)時(shí)器和支持產(chǎn)品 5V/3.3V 32-1250Mbps AnyRate Clock and Data Recovery RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
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SY87702L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AnyRate? CDR