參數(shù)資料
型號(hào): SY87701VZH
廠商: Micrel Inc
文件頁(yè)數(shù): 11/15頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY 28-SOIC
標(biāo)準(zhǔn)包裝: 27
系列: AnyRate®
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,ATM 應(yīng)用
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.25Gbps
電源電壓: 3.15 V ~ 5.25 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1089 (CN2011-ZH PDF)
其它名稱: 576-2118-5
576-2118-5-ND
576-2969-5
SY87701V
5
Micrel, Inc.
M9999-073008
hbwhelp@micrel.com or (408) 955-1690
CHARACTERISTICS
Performance
The SY87701V PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and
ITU-T Recommendations: G.958 document, when used with
differential inputs and outputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal that
causes an equivalent 1dB optical/electrical power penalty.
SONET input jitter tolerance requirement condition is the
input jitter amplitude which causes an equivalent of 1dB
power penalty.
Figure 1. Input Jitter Tolerance
OC/STS-N
f0
f1
f2
f3
ft
Level
(Hz)
(kHz)
3
10
30
300
6.5
65
12
10
30
300
25
250
15
1.5
0.40
f0
f1
f2
f4
ft
Sinusoidal
Input
Jitter
Amplitude
(UI
p-p)
Frequency
-20dB/decade
A
Figure 2. Jitter Transfer
OC/STS-N
fc
P
Level
(kHz)
(dB)
3
130
0.1
12
225
0.1
0.1
-20
fc
Jitter Transfer (dB)
Frequency
-20dB/decade
Acceptable
Range
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on the
input OC-N/STS-N signal versus frequency. Jitter transfer
requirements are shown in Figure 2.
Jitter Generation
The jitter of the serial clock and serial data outputs shall
not exceed .01 U.I. rms when a serial data input with no
jitter is presented to the serial data inputs.
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