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參數(shù)資料
| 型號： | SY87724L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| 中文描述： | 3.3 AnyRate復用/解復用器高達2.7GHz的 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 103K |
| 代理商： | SY87724L |
SY87724L
FINAL
6
Micrel
DESCRIPTION
General
The SY87724L MDM is designed to perform muxing and
demuxing at up to 2.7GHz speeds. The device can
simultaneously mux and demux up to 10 bits of full duplex
data. In addition, a full parallel-to-parallel loopback function
is implemented, such that parallel data out will loop back to
parallel data in, with the device internally connecting the
serial output to the serial input.
Narrow Demux
In this example, serial data is converted into 4 or 5 bit
wide data. Because this can result in very high data rates
on the parallel outputs, they are differential. The DFMIN
±
input indicates, synchronously with DCKIN
±
, and one clock
ahead, the start of a 4 or 5 bit boundary.
MDM
DP0-4
±
DPOUTCK
±
DSIN
±
DCKIN
±
DFMIN
±
Figure 1. Narrow Demux
Every DFMIN
±
assertion will trigger a new 4 or 5 bit
boundary. Should only one DFMIN
±
assertion occur, then
DPOUTCK
±
will continue to assert every 4 or 5 DCKIN
±
clocks. Should a subsequent DFMIN
±
assertion reset the 4
or 5 bit boundary, then DPOUTCK
±
will always result in a
longer assertion, not a shorter one.
For example, if a subsequent DFMIN
±
resets a 5 bit
boundary after the second bit in relation to a previous
boundary, then the next DPOUTCK
±
will always occur 7
DCKIN
±
later, never 2 DCKIN
±
later. For four bit output,
DP5
±
are not used.
Wide Demux
The more typical case will be to convert the serial data
stream into 8 or 10 bit wide data. Because the worst case
parallel transfer rate is on the order of 250 to 340 Mega-
transfers per second, single ended parallel output is
preferred. Thus, only the single-ended side of the differential
outputs is used.
This example is much like the narrow demux, except
now DFMIN
±
indicates 8 or 10 bit boundaries.
MDM
DP0-4+
DPOUTCK+
DSIN
±
DCKIN
±
DFMIN
±
DP5-9
Figure 2. Wide Demux
As in the narrow case, DPOUTCK
±
will never assert
twice in 8 or 10 DCKIN
±
cycles. Should a DFMIN
±
assertion
change the MDM
’
s 8 or 10 bit boundary, DPOUTCK
±
assertion will be delayed and there will never be a short
assertion.
For 8 bit output, DP4
±
and DP9 are not used.
The following table summarizes the available bit widths.
The right column shows the parallel bits, in sequence from
first in serially, to last in.
Width
4
5
8
10
Sequence
DP0
±
, DP1
±
, DP2
±
, DP3
±
DP0
±
, DP1
±
, DP2
±
, DP3
±
, DP4
±
DP0+, DP1+, DP2+, DP3+, DP5, DP6, DP7, DP8
DP0+, DP1+, DP2+, DP3+, DP4+, DP5, DP6, DP7,
DP8, DP9
Narrow Mux
In this scenario, 4 or 5 bit wide parallel data is converted
to a serial bit stream. Because this can result in very high
data rates on the parallel inputs, they are differential. In this
mode of operation, there is no external synchronization,
and the MPINCK
±
signal pair has arbitrary phase with
respect to the MTXCLK
±
clock, which clocks the mux output
shift register.
MDM
MSOUT
±
MPF0-4
±
MPINCK
±
MTXCLK
±
Figure 4. Narrow Mux
MPINCK
±
indicates when MDM is ready to accept more
data. It is derived from MTXCLK
±
, with an arbitrary phase
relationship.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SY87724L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724LE | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate?? MUX/DEMUX Up to 2.7GHz |
| SY87724LH1 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
| SY87724LHEI | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V AnyRate MUX/DEMUX Up to 2.7GHz |
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