參數(shù)資料
型號(hào): SY87724LH1
廠(chǎng)商: MICREL INC
元件分類(lèi): 數(shù)字傳輸電路
英文描述: 3.3V AnyRate MUX/DEMUX Up to 2.7GHz
中文描述: MUX/DEMUX, PQFP80
封裝: LQFP-80
文件頁(yè)數(shù): 5/13頁(yè)
文件大小: 103K
代理商: SY87724LH1
SY87724L
FINAL
5
Micrel
DEMUX
DSIN
±
Differential HSPC Input
This is the serial input to the SY87724L demux. It accepts
the serial data and converts it to parallel data. It is ignored
during loopback.
DCKIN
±
Differential HSPC Input
This is the bit rate clock that feeds serial data into the
demux shift register. This signal also feeds the demux strobe
generator and primary divider, except during loopback.
DFMIN
±
Differential HSPC Input
This is the frame alignment input signal. This signal resets
the primary divider, as well as the strobe generator. This
effectively sets the alignment for the parallel data being
demuxed. Usually, DFMIN
±
asserts one DCKIN
±
before a
parallel word boundary, and continues to assert one clock
before every boundary. However, DFMIN
±
need only occur
once for proper operation. Should DFMIN
±
assert at other
than a previously set boundary, the DPOUTCK
±
signal will
always occur later than would be expected. That is, there
will never be a short DPOUTCK
±
pulse.
DP0
±
through DP4
±
Differential PECL Output
These signals may be used as either differential, or single-
ended. When converting to 4 or 5 bits, speed issues may
encourage the use of these signals differentially. When
converting to wider than 5 bits, these signals are to be used
single-ended. Please refer to the applications section for
further details.
DP5 through DP9
PECL Output
These are the rest of the parallel output bits, to be used
when converting to wider than 5 bits. Which bits are valid
depends on the values of SIZ0, SIZ1, and SIZ2. Please
refer to the table in the applications section for further details.
DPOUTCK
±
Differential HSPC Output
This signal is used to strobe the DP0-9 data. It is used
differentially when converting to 4 or 5 bits, and is used
single-ended when converting to wider than 5 bits. The
clock rate of the line will be determined by the DCKIN
signal, and by the setting of the SIZ bits. This output always
provides valid differential logic levels.
MUX
MP0-9
PECL Input
These bits accept data for muxing wider than 5 bits.
MPINCK+, used single-ended, determines when this data
may change. Please refer to the table in the description for
which pins represent what bits for various widths.
MPF0
4
±
Differential PECL Input
These signals are used when muxing 4 or 5 bits of parallel
data. MPINCK
±
determines when this data may change.
Please refer to the Mux table in the description for which
pins represent what bits for various widths.
MTXCLK
±
Differential HSPC Input
This is the serial rate clock input to the mux. It determines
the rate at which serial data will be shifted out of the mux.
MSOUT
±
Differential PECL Output
This signal is the serialized data output.
MPINCK
±
Differential PECL Output
This signal indicates when the next set of parallel bits
may be presented to the SY87724L for muxing. For muxing
wider than 5 bits, MPINCK+ is used single-ended. These
signals always provide valid differential clock signals
regardless of single-ended or differential data mode.
OTHER
V
CC
V
CCO
GND
NC
Supply Voltage
Output Supply Voltage
Ground
These pins are reserved and are to be left
unconnected.
Note:
1. All differential outputs always provide valid differential logic levels regardless
of differential or single-ended use.
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