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參數(shù)資料
| 型號： | SY88149NDLMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIMITING AMP 1.25GBPS 16QFN |
| 特色產(chǎn)品： | SY88149NDL Limiting Post Amplifier |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 限幅后置放大器 |
| 應(yīng)用： | 光纖學(xué)網(wǎng)絡(luò) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 576-4003-6 |
Micrel, Inc.
SY88149NDL
February 2012
3
M9999-020712-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
DIN, /DIN
Differential Data Inputs. If AC-coupled, terminate each pin to VREF with 50.
2
VREF
Reference Voltage Output. Typically VCC – 1.3V.
3, 11, 8
GND
Device Ground. Exposed pad must be soldered (or equivalent) to the same potential as the
ground pins.
10
/AUTO RESET
LVTTL Input. This pin is internally connected to a 25k pull-up resistor and defaults to HIGH.
When this pin is LOW or tied to ground, the /AUTO RESET function is enabled and SD deasserts
or LOS asserts within 120ns (typical) after the last high-to-low transition of the burst input. When
this pin is left floating or tied high, the AUTO RESET function is disabled and the SD deassert or
LOS assert must be forced by using the manual RESET function.
5, 16
VCC
Positive power supply. Bypass with 0.1uF | | 0.01uF low ESR capacitors. 0.01uF capacitors
should be as close as possible to VCC pins.
6
RESET
LVTTL Input. Apply a high-level signal (
>2V) to this pin to reset the SD deassert time or LOS
assert within 5ns. RESET defaults to LOW if left floating. If the /AUTO RESET function is not
used, this RESET function needs to be used to quickly deassert the SD or assert LOS. This pin
is internally connected to a 25k pull-down resistor and defaults to LOW.
7
SD/LOS
LVTTL Output. Signal detect (SD) asserts high when the data input amplitude rises above the
threshold sets by SDLVL. Conversely, loss-of-signal (LOS) deasserts low when the data input
amplitude rises above the threshold set by LOS/SDLVL.
12, 9
DOUT, /DOUT
LVPECL Outputs. When JAM disables the device, output DOUT is forced to logic LOW and
output /DOUT is forced to logic HIGH.
13
LOS/SD SEL
Allows the user to select between whether LOS or SD is outputted on the LOS/SD pin. Also
controls the polarity of the JAM input. When SD is selected, JAM is active HIGH and LOS/SD
(Pin 7) operates as signal detect. Conversely, when LOS is selected, JAM is active LOW and
LOS/SD operates as loss-of-signal. This pin is internally connected to a 25k pull-up resistor
and defaults to HIGH (SD output selected).
14
LOS/SDLVL
Voltage Input. Sets the LOS/SD level. A resistor from this pin to VCC sets the threshold for the
data input amplitude at which LOS/SD will be asserted.
15
JAM
LVTTL Input. This JAM input acts as a squelch function and switches its polarity depending on
LOS/SD SEL status. When LOS is selected, this pin is active LOW. When SD is selected, this
pin is Active HIGH. To create a squelch function, connect JAM to LOS/SD. When JAM disables
the device, output Q is forced to logic LOW and output /Q is forced to logic HIGH. Note that this
input is internally connected to a 25k pull-up resistor.
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