參數(shù)資料
型號: SY88305BLEY TR
廠商: Micrel Inc
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC AMP CML LIMITING POST 10MSOP
標準包裝: 1,000
放大器類型: 限制
電路數(shù): 1
輸出類型: 差分
電流 - 電源: 38mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 10-MSOP 裸露焊盤
包裝: 帶卷 (TR)
Micrel, Inc.
SY88305BL
November 2007
7
M9999-110207-A
hbwhelp@micrel.com or (408) 955-1690
Functional Block Diagram
Detailed Description
The SY88305BL low-power limiting post amplifiers
operate from a single +3.3V power supply, over
temperatures from –40
oC to +85oC. Signals with data
rates up to 3.2Gbps and as small as 10mVPP can be
amplified. Figure 1 shows the allowed input voltage
swing. The SY88305BL generates an SD output
allowing feedback to EN for output stability. SDLVL sets
the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input
stage. The high-sensitivity of the input amplifier allows
signals as small as 10mVPP to be amplified. The input
amplifier
also
allows
input
signals
as
large
as
1800mVPP. Input signals below 12mVpp are linearly
amplified with a typical 42dB differential voltage gain.
Since it is a limiting amplifier, these devices output
typically 800mVPP voltage-limited waveforms for input
signals greater than 12mVPP. Applications requiring the
SY88305BL to operate with strong signals should have
the upstream TIA placed as close as possible to the
devices’ input pins. This ensures the best performance
of the device.
Output Buffer
The SY88305BL CML output buffers are designed to
drive 50
lines. The output buffer requires appropriate
termination for proper operation. An external 50
resistor to VCC for each output pin provides this. Figure 3
shows a simplified schematic of the output stage.
Signal Detect
The SY88305BL generates a chatter-free SD open-
collector TTL output, as shown in Figure 4. SD asserts
high if the input amplitude rises above the threshold sets
by SDLVL and de-asserts low otherwise. The SD output
can be fed back to the EN input to maintain stability
Signal-Detect Level Set
Programmable SD level set pin (SDLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and SDLVL set the
voltage at SDLVL. This voltage ranges from VCC to VREF.
The external resistor creates a voltage divider between
VCC and VREF, as shown in Figure 5.
Hysteresis
The SY88305BL typically provides 3.5dB SD electrical
hysteresis. By definition, a power ratio measured in dB
is 10log (power ratio). Power is calculated as V
2
IN/R for
an electrical signal. Hence, the same ratio can be stated
as 20log (voltage ratio). While in linear mode, the
electrical voltage input changes linearly with the optical
power and therefore, the ratios change linearly. Thus,
the optical hysteresis in dB is half the electrical
hysteresis in dB given in the datasheet. Since the
SY88305BL are electrical devices, this data sheet refers
to hysteresis in electrical terms. With 3.5dB SD
hysteresis, a voltage factor of 1.5 is required to assert or
de-assert SD.
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