V
參數(shù)資料
型號: SY88315BLEY
廠商: Micrel Inc
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC POST AMP CML LP LIMIT 10-MSOP
標準包裝: 100
類型: 限幅后置放大器
應用: 光纖學網(wǎng)絡
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應商設備封裝: 10-MSOP 裸露焊盤
包裝: 管件
Micrel, Inc.
SY89851U
July 2005
M9999-071205
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics
(7)
VCC = 2.5V ±5% or 3.3V ±10%, RL = 50
to V
CC –2V, VIN
100mV (200mV
PP); TA = –40°C to + 85°C, unless
otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
NRZ Data
2.5
3.5
Gbps
Clock
3
4
GHz
tpd
Differential Propagation Delay
IN-to-Q
140
220
340
ps
tpd Tempco
t
pd Temperature Coefficient
130
fs/°C
tSKEW
Output-to-Output Skew
Part-to-Part Skew
Note 8
Note 9
6
20
120
ps
tJITTER
Data
Random Jitter
Note 10
1
psRMS
Deterministic Jitter
Note 11
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 12
1
psRMS
Total Jitter
Note 13
10
psPP
tr, tf
Output Rise/Fall Time (20% to 80%)
At full output swing
50
100
180
ps
Notes:
7.
High-frequency AC-parameters are guaranteed by design and characterization.
8.
Output-to-output skew is measured between two different outputs under identical input transitions.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew
of the edges at the respective inputs.
10. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps.
11. Deterministic jitter is measured at 2.5Gbps, with both K28.5 and 2
23 – 1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between
rising edges of the output signal.
13. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will
deviate by more than the specified peak-to-peak jitter value.
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