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參數(shù)資料
型號: SY88347DLEY
廠商: Micrel Inc
文件頁數(shù): 7/9頁
文件大?。?/td> 0K
描述: IC POST AMP PECL 3.2GBPS 10-MSOP
標準包裝: 100
類型: 限幅后置放大器
應用: 光纖學網(wǎng)絡
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應商設備封裝: 10-MSOP 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1504
Micrel, Inc.
SY88347DL
February 2007
7
M9999-021707-B
hbwhelp@micrel.com or (408) 955-1690
Functional Block Diagram
Detailed Description
The SY88347DL low-power, high-sensitivity limiting post
amplifier operates from a single +3.3V power supply,
over temperatures from –40
oC to +85oC. Signals with
data rates up to 3.2Gbps and as small as 5mVPP can be
amplified. Figure 1 shows the allowed input voltage
swing. The SY88347DL generates a LOS output
allowing feedback to /EN for output stability. LOSLVL sets
the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the
SY88347DL’s input stage. The high-sensitivity of the
input amplifier allows signals as small as 5mVPP to be
detected and amplified. The input amplifier also allows
input signals as large as 1800mVPP. Input signals are
linearly amplified with a typical 42dB differential voltage
gain. Since it is a limiting amplifier, the SY88347DL
outputs typically 1500mVPP voltage-limited waveforms
for input signals that are greater than 12mVPP.
Applications requiring the SY88347DL to operate with
high-gain should have the upstream TIA placed as close
as possible to the SY88347DL’s input pins. This ensures
the best performance of the device.
Output Buffer
The SY88347DL’s PECL output buffer is designed to
drive 50 lines. The output buffer requires appropriate
termination for proper operation. An external 50
resistor to VCC-2V for each output pin provides this.
Figure 3 shows a simplified schematic of the output
stage.
Loss-of-Signal
The SY88347DL generates a chatter-free LOS open-
collector TTL output, as shown in Figure 4. LOS is used
to determine that the input amplitude is large enough to
be considered a valid input. LOS asserts high if the input
amplitude falls below the threshold sets by LOSLVL and
de-asserts low otherwise. LOS can be fed back to the
enable bar (/EN) input to maintain output stability under
a loss-of-signal condition. /EN de-asserts the true output
signal without removing the input signals. Typically,
3.3dB LOS hysteresis is provided to prevent chattering.
Loss-of-Signal Level Set
A programmable LOS level set pin (LOSLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and LOSLVL sets the
voltage at LOSLVL. This voltage ranges from VCC to VREF.
The external resistor creates a voltage divider between
VCC and VREF, as shown in Figure 5.
Hysteresis
The SY88347DL typically provides 3.3dB LOS electrical
hysteresis. By definition, a power ratio, measured in dB,
is 10log (power ratio). Power is calculated as V
2
IN/R for
an electrical signal. Hence, the same ratio can be stated
as 20log (voltage ratio). While in linear mode, the
electrical voltage input changes linearly with the optical
power and therefore, the ratios will change linearly.
Thus, the optical hysteresis in dB is half the electrical
hysteresis in dB given in the data sheet. Since the
SY88347DL is an electrical device, this data sheet
refers to hysteresis in electrical terms. With 3.3dB LOS
hysteresis, a voltage factor of 1.46 is required to assert
or de-assert LOS.
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SY88347DLEYTR 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 3.2Gbps PECL Limiting Post Amplifier with High-Gain TTL Loss-of-Signal
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