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參數(shù)資料
| 型號(hào)： | SY88813VKGTR |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V/5V 155Mbps PECL LOW POWER LIMITING POST AMPLIFIER WITH PECL SIGNAL DETECT |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MSOP-10 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 56K |
| 代理商： | SY88813VKGTR |
5
SY88813V
Micrel, Inc.
M9999-072505
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88813V low power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from
–
40
°
C to +85
°
C. Signals with data rates up to 155Mbps
and as small as 5mV
PP
can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88813V generates
a SD output. SD
LVL
sets the sensitivity of the input amplitude
detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the SY88813V's
input stage. The high-sensitivity of the input amplifier allows
signals as small as 5mV
PP
to be detected and amplified.
The input amplifier allows input signals as large as
1800mV
PP
. Input signals are linearly amplified with a typically
38dB differential voltage gain. Since it is a limiting amplifier,
the SY88813V outputs typically 1500mV
PP
voltage-limited
waveforms for input signals that are greater than 18mV
PP
.
Applications requiring the SY88813V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88813V
’
s input pins to ensure the best
performance of the device.
Output Buffer
The SY88813V
’
s PECL output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC
–
2V
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
Signal-Detect
The SY88813V generates a chatter-free PECL SD similar
to the SY88813V's output buffer. SD is used to determine
that the input amplitude is large enough to be considered a
valid input. SD asserts high if the input amplitude rises
above the threshold set by SD
LVL
and deasserts low
otherwise. /EN deasserts the true output signal without
removing the input signals. Typically 4.6dB SD hysteresis is
provided to prevent chattering.
Signal-Detect Level Set
A programmable signal-detect level set pin (SD
LVL
) sets
the threshold of the input amplitude detection. Setting a
voltage on SD
LVL
between V
CC
and V
REF
sets this threshold.
If desired, a resistor divider between V
CC
and V
REF
, as
shown in Figure 4, also creates this threshold. The smaller
the voltage difference from SD
LVL
to V
CC
, the smaller the
SD sensitivity. Hence, larger input amplitude is required to
assert SD.
“
Typical Operating Characteristics
”
shows the
relationship between the input amplitude detection sensitivity
and the SD
LVL
voltage.
Hysteresis
The SY88813V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V
2IN
/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88813V provides typically 2.3dB
SD optical hysteresis. As the SY88813V is an electrical
device, this datasheet refers to hysteresis in electrical terms.
With 6dB SD hysteresis, a voltage factor of two is required
to assert or deassert SD.
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