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參數(shù)資料
| 型號： | SY88883VKG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 0K |
| 描述： | IC POST AMP CML LP LIMIT 10-MSOP |
| 標準包裝： | 1,000 |
| 類型： | 限幅后置放大器 |
| 應用： | 光纖學網(wǎng)絡(luò) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY88883VKGTR SY88883VKGTR-ND |
5
SY88883V
Micrel, Inc.
M9999-081005
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88883V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40
°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mVPP can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88883V generates
an SD output. SD
LVL sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
The SY88883V’s inputs are internally terminated with 50
to an internal reference voltage (V
REF). VREF is typically
1.3V below V
CC. Unless not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88883V’s inputs. Figure 2 shows a
simplified schematic of the input stage.
The high-sensitivity of the input amplifier allows signals
as small as 10mVPP to be detected and amplified. The
input amplifier allows input signals as large as 1800mVPP.
Input signals are linearly amplified with a typically 38dB
differential voltage gain. Since it is a limiting amplifier, the
SY88883V outputs typically 800mVPP voltage-limited
waveforms for input signals that are greater than 10mVPP.
Applications requiring the SY88883V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88883V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88883V’s CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50
to V
CC eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mVPP waveforms across 25 total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Signal Detect
The SY88883V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5k
pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude large enough to be considered a valid
input. SD asserts high if the input amplitude rises above the
threshold set by SD
LVL and deasserts low otherwise.
Typically 4.6dB SD hysteresis is provided to prevent
chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC and SDLVL sets the voltage
at SD
LVL. This voltage ranges from VCC to VREF. The
external resistor creates a voltage divider between V
CC and
V
REF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL to VCC, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL setting resistor.
Hysteresis
The SY88883V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and,
hence, the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88883V provides typically 2.3dB
SD optical hysteresis. As the SY88883V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its deassert level.
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| SY88883VKI | 功能描述:IC AMP LIMIT PECL TTL SIG 10MSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| SY88883VKI TR | 功能描述:IC AMP POST PECL 3.3V/5V 10-MSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| SY88893V | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V/5V 155Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/TTL SIGNAL DETECT |
| SY88893VKC | 功能描述:IC AMP POST PECL 3.3V/5V 10-MSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| SY88893VKC TR | 功能描述:IC AMP POST PECL 3.3V/5V 10-MSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
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