參數(shù)資料
型號(hào): SY88883VKG
廠商: Micrel Inc
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 0K
描述: IC POST AMP CML LP LIMIT 10-MSOP
標(biāo)準(zhǔn)包裝: 100
類(lèi)型: 限幅后置放大器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
1
SY88883V
Micrel, Inc.
M9999-081005
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s Multi-rate up to 3.2Gbps operation
s Wide gain-bandwidth product
38dB differential gain
2.2GHz 3dB bandwidth
s Low noise 50
CML data outputs
800mVPP output swing
60ps edge rates
5ps
RMS typ. random jitter
15psPP typ. deterministic jitter
s Chatter-free Signal Detect (SD) output
4.6dB electrical hysteresis
OC-TTL output with internal 5k
pull-up resistor
s Programmable SD sensitivity using single external
resistor
s Internal 50
data input termination
s Wide operating range
Single 3.3V
±10% or 5V ±10% power supply
–40
°C to +85°C industrial temperature range
s Available in a tiny 10-pin MSOP (3mm
××××× 3mm)
package
FEATURES
3.3V/5V 3.2Gbps CML LOW-POWER
LIMITING POST AMPLIFIER WITH TTL SD
SY88883V
APPLICATIONS
s 1.25Gbps and 2.5Gbps Gigabit Ethernet
s 1.062Gbps and 2.125Gbps Fibre Channel
s 155Mbps, 622Mbps, 1.25Gbps and 2.5Gbps
SONET/SDH
s Gigabit interface converter (GBIC)
s Small form factor (SFF) and small form factor
pluggable (SFP) transceivers
s Parallel 10G Ethernet
s High-gain line driver and line receiver
Rev.: B
Amendment: /0
Issue Date:
August 2005
The SY88883V low-power, limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88883V
quantizes these signals and outputs typically 800mVPP
voltage-limited waveforms.
The SY88883V operates from a single +3.3V
±10% or
+5V
±10% power supply, over the industrial temperature
range of –40
°C to +85°C. With its wide bandwidth and high-
gain, signals with data rates up to 3.2Gbps and as small as
10mVpp can be amplified to drive devices with CML inputs
or AC-coupled PECL inputs.
The SY88883V generates a signal detect (SD) open-
collector TTL output with internal 5k
pull-up resistor. A
programmable signal detect level set pin (SD
LVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SD
LVL
and de-asserts low otherwise. Typically 4.6dB SD hysteresis
is provided to prevent chattering.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
TYPICAL PERFORMANCE
FUNCTIONAL BLOCK DIAGRAM
Limiting
Amplifer
CML
Buffer
GND
2.8k
50
Level
Detect
SD
DIN
/DIN
VCC
SDLVL
DOUT
/DOUT
5k
OC-TTL
Buffer
VCC
–1.3V
3.3V, 25
°C, 10mV
PP Input
@2.5Gbps 223–1 PRBS, RLOAD = 50 to VCC
TIME (100ps/div.)
Output
Swing
(75mV/div
.)
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