參數(shù)資料
型號(hào): SY88923AVKG TR
廠商: Micrel Inc
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 0K
描述: IC POST AMP HS LIMITING 10-MSOP
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: 限幅后置放大器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)
安裝類(lèi)型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
其它名稱(chēng): SY88923AVKGTR
SY88923AVKGTR-ND
1
SY88923AV
Micrel, Inc.
M9999-110905
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s Single 3.3V or 5V power supply
s Up to 3.2Gbps operation
s Low noise PECL data outputs
s Chatter-free open collector TTL LOS output
s TTL /EN Input
s Differential PECL inputs for data
s Available in a tiny 10-pin (3mm) MSOP and 10-pin
(3mm) EPAD-MSOP
The SY88923AV limiting post amplifier with its high
gain and wide bandwidth is ideal for use as a post
amplifier in fiber-optic receivers with data rates up to
3.2Gbps. Signals as small as 5mV
PP can be amplified
to drive devices with PECL inputs. The SY88923AV
generates a chatter-free Loss-of-Signal (LOS) open
collector TTL output.
The SY88923AV incorporates a programmable level
detect function to identify when the input signal has been
lost. The LOS output will change from logic “LOW” to logic
“HIGH” when input signal is smaller than the swing set by
LOSLVL. This information can be fed back to the EN input
of the device to maintain stability under loss-of-signal
condition. Using LOSLVL pin, the sensitivity of the level
detection can be adjusted. The LOSLVL voltage can be set
by connecting a resistor divider between VCC and VREF
shown in Figure 3. “Typical Operating Characteristics” on
page 6 show the relationship between input level sensitivity
and the voltage set on LOSLVL.
The LOS output is a TTL open collector output that
requires a pull-up resistor for proper operation, Figure 1.
SY88923AV
LOS
4.7k
to 10k
VCC
Figure 1. LOS Output with Desired Rise Time
FEATURES
5V/3.3V 3.2Gbps HIGH-SPEED
LIMITING POST AMPLIFIER
SY88923AV
APPLICATIONS
s 1.25Gbps and 2.5Gbps Gigabit Ethernet
s 531Mbps, 1062Mbps and 2.12Gbps Fibre Channel
s 622Mbps SONET
s Gigabit interface converter
s 2.5Gbps SDH/SONET
s 2.5Gbps proprietary links
s Parallel 10G Ethernet
BLOCK DIAGRAM
Limiting
Amplifer
ECL
Buffer
GND
Enable
Level
Detect
/EN
LOS
DIN
/DIN
VREF
VCC
LOSLVL
DOUT
/DOUT
Rev.: F
Amendment: /0
Issue Date:
November 2005
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