參數(shù)資料
型號: SY88923VKG
廠商: Micrel Inc
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC POST AMP HS LIMITING 10-MSOP
標(biāo)準包裝: 100
類型: 限幅后置放大器
應(yīng)用: 光纖學(xué)網(wǎng)絡(luò)
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
產(chǎn)品目錄頁面: 1090 (CN2011-ZH PDF)
其它名稱: 576-2075-5
SY88923VKG-ND
1
SY88923V
Micrel, Inc.
M9999-051706
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
s 3.3V and 5V power supply options
s Up to 2.5Gbps operation
s Low noise
s Chatter-Free LOS Generation
s Open Collector TTL LOS Output
s TTL /EN Input
s Differential PECL inputs for data
s Single power supply
s Designed for use with Micrel's Laser Diode Driver
and Controller
s Available in a tiny 10-pin (3mm) MSOP
The SY88923V limiting post amplifier with its high gain
and wide bandwidth is ideal for use as a post amplifier in
fiber-optic receivers with data rates up to 2.5Gbps.
Signals as small as 5mV
PP can be amplified to drive
devices with PECL inputs. The SY88923V generates a
chatter-free Loss of Signal (LOS) open collector TTL
output.
The SY88923V incorporates a programmable level detect
function to identify when the input signal has been lost.
The LOS output will change from logic “LOW” to logic
“HIGH” when input signal is smaller than the swing set by
LOS
LVL. This information can be fed back to the EN input
of the device to maintain stability under loss of signal
condition. Using LOS
LVL pin, the sensitivity of the level
detection can be adjusted. The LOS
LVL voltage can be set
by connecting a resistor divider between V
CC and VREF
show in Figure 3. Performance Curves show the relationship
between input level sensitivity and the voltage set on
LOS
LVL.
The LOS output is a TTL open collector output that
requires a pull-up resistor for proper operation, Figure 1.
FEATURES
5V/3.3V 2.5Gbps HIGH-SPEED
LIMITING POST AMPLIFIER
SY88923V
APPLICATIONS
s 1.25Gbps and 2.5Gbps Gigabit Ethernet
s 531Mbps, 1062Mbps and 2.12Gbps Fibre Channel
s 622Mbps SONET
s Gigabit Interface Converter
s 2.5Gbps SDH/SONET
s 2.5Gbps Proprietary Links
BLOCK DIAGRAM
Figure 1. LOS Output with Desired Rise Time
SY88923V
LOS
2.5k
VCC
Limiting
Amplifer
ECL
Buffer
GND
Enable
Level
Detect
/EN
LOS
DIN
/DIN
VREF
VCC
LOSLVL
DOUT
/DOUT
Rev.: E
Amendment: /0
Issue Date:
May 2006
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