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參數(shù)資料
| 型號(hào)： | SY89200UTR |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 X 5 MM, MLF-32 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | SY89200UTR |
2
SY89200U
Micrel
M9999-061704
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Package
Part Number
Type
Range
Marking
SY89200U
MLF-32
Industrial
SY89200U
SY89200UTR(2)
MLF-32
Industrial
SY89200U
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C,
DC Electricals Only.
2. Tape and Reel.
Pin Number
Pin Name
Pin Function
3, 6
IN, /IN
Differential Input: This input pair is the differential signal input to the device. This input
accepts AC- or DC-coupled signals as small as 100mV. The input pair internally terminates
to a VT pin through 50
. Note that these inputs will default to an indeterminate state if left
open. Please refer to the “Input Interface Applications” section for more details.
2
DIVSEL1
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the three
7
DIVSEL2
banks of outputs. Note that each of these inputs is internally connected to a 25k
pull-up
8
DIVSEL3
resistor and will default to a logic HIGH state if left open. The input switching threshold is
VCC/2.
4
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “Input Interface Applications” section for more details.
5
VREF-AC
Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs IN
and /IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass with
0.01
F low ESR capacitor to V
CC. Maximum sink/source capability is 0.5mA.
9
EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0 – Q7 outputs. This
input is internally connected to a 25k
pull-up resistor and will default to a logic HIGH state
if left open.The input switching threshold is VCC/2. For the input enable and disable func-
tional description, refer to Figures 2a through 2c.
30, 29, 28,
Q0, /Q0, Q1,
Bank 1 LVDS differential output pairs controlled by DIVSEL1: LOW, Q0 – Q3 =
÷1, HIGH,
27, 26, 25,
/Q1, Q2, /Q2,
Q0 – Q3 =
÷2. Unused output pairs should be terminated with 100 across the differential
24, 23
Q3, /Q3
pair.
16, 15, 14,
Q4, /Q4, Q5,
Bank 2 LVDS differential output pairs controlled by DIVSEL2: LOW, Q4 – Q6 =
÷2, HIGH,
13, 12, 11
/Q5, Q6, /Q6
Q4 – Q6 =
÷4. Unused output pairs should be terminated with 100 across the differential
pair.
18, 17
Q7, /Q7
Bank 3 LVDS differential output pair controlled by DIVSEL3: LOW, Q7 =
÷2, HIGH,
Q7 =
÷4. Unused output pair should be terminated with 100 across the differential pair.
32
/MR
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets
Q0 – Q7 outputs LOW, /Q0 – /Q7 outputs HIGH, and holds them in that state as long as
/MR remains LOW. This input is internally connected to a 25k
pull-up resistor and will
default to a logic HIGH state if left open. The input switching threshold is VCC/2.
10, 19, 22, 31
VCC
Positive power supply. Bypass with 0.1
F0.01F low ESR capacitors.
1, 20, 21
GND,
Ground and exposed pad must be connected to the same GND plane on the board.
Exposed Pad
PIN DESCRIPTION
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 1213141516
32 3130 29 28 27 26 25
GND
DIVSEL1
IN
VT
VREF-AC
/IN
DIVSEL2
DIVSEL3
Q3
/Q3
VCC
GND
VCC
Q7
/Q7
Q1
/Q0
Q0
VCC
/MR
/Q1
Q2
/Q2
/Q5
Q6
/Q6
VCC
EN
Q5
/Q4
Q4
32-Pin MLF (MLF-32)
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