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參數(shù)資料
| 型號(hào)： | SY89202UMG |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF DVDR MUX 1:8 32-MLF |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），除法器，多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，PECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 1.5GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1083 (CN2011-ZH PDF) |
| 其它名稱： | 576-1537-5 SY89202UMG-ND |
Micrel, Inc.
SY89202U
August 2007
4
M9999-083107-C
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
2, 7, 8
DIVSEL1
DIVSEL2
DIVSEL3
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the three
banks of outputs. Note that each of these inputs is internally connected to a 25k
pull-up
resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2.
3, 6
IN, /IN
Differential Input: This input pair is the differential signal input to the device. This input accepts
AC- or DC-coupled signals as small as 100mV. The input pair internally terminates to a VT pin
through 50
. Note that these inputs will default to an indeterminate state if left open. Please
refer to the “Input Interface Applications” section for more details.
4
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin.
The VT pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section for more details.
5
VREF-AC
Reference Voltage: This output biases to VCC –1.2V. It is used for AC-coupling inputs IN and
/IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass with 0.01F
low ESR capacitor to VCC.
9
EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0 – Q7 outputs. This
input is internally connected to a 25k
pull-up resistor and will default to logic HIGH state if left
open. The input-switching threshold is VCC/2. For the input enable and disable functional
description, refer to “Timing Diagram” section.
10, 19, 22, 31
VCC
Positive power supply. Bypass with 0.1F||0.01F low ESR capacitors as close to VCC pins
as possible.
16, 15, 14,
13, 12, 11
Q4, /Q4, Q5,
/Q5, Q6, /Q6
Bank 2 LVPECL differential output pairs controlled by DIVSEL2: LOW, Q4 – Q6 = ÷2, HIGH,
Q4 – Q6 = ÷4. Unused output pairs may be left open. Each output is designed to drive 800mV
into 50
terminated at VCC–2V.
30, 29, 28,
27, 26, 25,
24, 23
Q0, /Q0, Q1,
/Q1, Q2, /Q2,
Q3, /Q3
Bank 1 LVPECL differential output pairs controlled by DIVSEL1: LOW, Q0 – Q3 = ÷1, HIGH,
Q0 – Q3 = ÷2. Unused output pairs may be left open. Each output is designed to drive 800mV
into 50
terminated at VCC–2V.
18, 17
Q7, /Q7
Bank 3 LVPECL differential output pair controlled by DIVSEL3: LOW, Q7 = ÷2, HIGH, Q7 =
÷4. Unused output pairs may be left open. Each output is designed to drive 800mV into 50
terminated at VCC–2V.
32
/MR
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets
Q0 – Q7 outputs LOW and /Q0 – /Q7 outputs HIGH, and holds them in that state as long as
the /MR input remains LOW. This input is internally connected to a 25k
pull-up resistor and
will default to a logic HIGH state if left open. The input-switching threshold is VCC/2.
1, 20, 21
GND,
Exposed Pad
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Truth Table
/MR
( 1)
EN
( 2, 3)
DIVSEL1
DIVSEL2
DIVSEL3
Q0 – Q3
Q4 – Q6
Q7
0
X
0
1
0
X
0
1
0
1
2
1
2
4
Notes:
1. /MR asynchronously forces Q0 – Q7 LOW (/Q0 - /Q7 HIGH).
2. EN forces Q0 – Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3. EN synchronously enables the outputs between 2 and 6 input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
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