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參數(shù)資料
| 型號(hào)： | SY89229UMG |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLK DIVIDER /3/5 LVDS 16-MLF |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘除法器 |
| PLL： | 無(wú) |
| 輸入： | CML，LVDS，PECL |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1083 (CN2011-ZH PDF) |
| 其它名稱： | 576-1651-5 |
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Micrel, Inc.
SY89229U
August 2007
M9999-080707-A
hbwhelp@micrel.com or (408) 955-1690
7
Functional Description
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below
100mVPK
(200mVPP),
typically
30mVPK.
Maximum frequency of the SY89229U is limited by the
FSI function. Refer to Figure 1b.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output
signal. No ringing and no undetermined state will
occur at the output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal as it nears the FSI threshold
(typically 30mV). Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. See “Typical
Operating Characteristics” for detailed information.
Output Duty Cycle Equation
For a non 50% input, derate the spec by:
For divide by 3:
(0.5 -
3
100
1
X
+
) x100, in %
For divide by 5:
(0.5 -
5
100
2
X
+
) x100, in %
X= input Duty Cycle, in %
Enable (EN)
EN is a synchronous TTL/CMOS-compatible input that
enables/disables the outputs based on the input to
this pin. Internal 25kΩ pull-up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is VCC/2.
The Enable function operates as follows:
1.
The
enable/disable
function
is
synchronous so that the clock outputs will
be enabled or disabled following a rising
and a falling edge of the input clock when
switching from EN = LOW to EN = HIGH.
However, when switching from EN = HIGH
to EN = LOW, the clock outputs will be
disabled following an input clock rising
edge and an output clock falling edge.
2.
The
enable/disable
function
always
guarantees the full pulse width at the
output
before
the
clock
outputs
are
disabled, non-depending on the divider
ratio.
Refer to Figure 1c for examples.
Divider Operation
The divider operation uses both the rising and falling
edge of the input clock. For divide by 3, the falling
edge of the second input clock cycle will determine
the falling edge of the output. For divide by 5, the
falling edge of the third input clock cycle.
Refer to
Figure 1d.
Example: if a 45% input duty cycle is applied or X=45,
in divide by 3 mode, the spec would expand by 1.67%
to 44.3%-55.7%
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89229UMG TR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (1GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89229UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:1GHz Precision, LVDS ÷3, ÷5 Clock Divider with Fail Safe Input and Internal Termination |
| SY89230U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:1GHz Precision, LVPECL ±3, ±5 Clock Divider with Fail-Safe Input and Internal Termination |
| SY89230U_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2GHz Precision, LVPECL ÷3, ÷5 Clock Divider |
| SY89230U-EVAL | 制造商:Micrel Inc 功能描述:DIVIDE-BY-3 AND 5 LVPECL CLOCK |
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