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參數(shù)資料
| 型號(hào)： | SY89230UMG |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIVIDER LVPECL 16-MLF |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘除法器 |
| PLL： | 無(wú) |
| 輸入： | CML，LVDS，PECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.2GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2112-5 576-2112-5-ND 576-2964-5 |
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CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
DS651UM23
Copyright 2005 Cirrus Logic, Inc.
13
Version 2.3
4.2.3 Synchronous Serial (Audio) Signals
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in "Digital Audio Interface" on page 19.
4.2.4 Audio Clock Signals
See "Synchronization" on page 17 for an overview of synchronization modes and issues.
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
DAO1_SCLK
Audio Bit Clock
Out
J3:A7
20
Synchronous serial bit clock.
64 FS for CS18100x & CS49610x (2x1 channel)
64 FS for CS18101x & CS49611x (2x4
channels)
128 FS for CS18102x & CS49612x (4x4
channels)
Typically tied to DAI1_SCLK.
DAO1_DATA[3:0]
Audio Output
Data
Out
J3:A18,
B18
15-17, 19
Output synchronous serial audio data
DAO1_DATA[3:1] not used for CS18100x &
CS49610x.
DAI1_DATA[3:0]
Audio Input Data
In
J3:
A[15:12]
131, 132, 134, 135
Input synchronous serial audio data
DAI1_DATA[3:1] not used for CS18100x &
CS49610x.
DAI1_SCLK
Audio Bit Clock
In
J4:A7
137
Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
DAI1_LRCLK
Sample clock
input
In
138
Should be tied to DAO1_LRCLK for all devices.
DAO1_LRCLK
(FS1)
Sample clock
output
Out
J3:A3
22
FS1 (word clock) for CS18100x/CS49610x and
CS18101x/CS49611x.
DAO2_LRCLK
(FS1)
Sample clock
output
Out
J3:A3
14
FS1 (word clock) for CS18102x & CS49612x.
REFCLK_IN
Reference clock
In
J3:A6
97
Clock input for synchronizing network to an
external clock source, for redundancy control
and synchronization of FS divider chain to
external source. See "Synchronization" on
page 17 for more detail.
MCLK_IN
Master audio
clock input
In
J3:A5
8*
For systems featuring multiple CobraNet
interfaces operating off a common master
clock. See "Synchronization" on page 17 for
more detail.
MCLK_OUT
Master audio
clock output
Out
J3:A4
8*
Low jitter 24.576 MHz master audio clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89230UMG TR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVPECL Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89230UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2GHz Precision, LVPECL ÷3, ÷5 Clock Divider |
| SY89231U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:1GHz Precision, LVPECL ±3, ±5 Clock Divider with Fail-Safe Input and Internal Termination |
| SY89231UMG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89231UMG TR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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