- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98150 > SY89231UMG (MICREL INC) 89231 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 PDF資料下載
參數(shù)資料
| 型號(hào)： | SY89231UMG |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 89231 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, QFN-16 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 419K |
| 代理商： | SY89231UMG |
Micrel, Inc.
SY89231U
November 2007
M9999-110507-A
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics
(8)
VCC = 2.5V ±5%; RL = 100
across the outputs; T
A = –40°C to + 85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Input Operating
Frequency
VOUT
≥ 200mV
3.2
4.5
GHz
tw
Minimum Pulse Width
IN, /IN
140
ps
tpd
Differential Propagation Delay
In-to-Q
410
610
810
ps
/MR(H-L)-to-Q
210
410
610
ps
tRR
Reset Recovery Time
/MR(L-H)-to-IN
400
ps
tS EN
Set-up Time
EN-to-IN
Note 9
50
ps
tH EN
Hold Time
IN-to-EN
Note 9
250
ps
tskew
Part-to-Part Skew
Note 10
300
ps
tJITTER
Clock
Random Jitter
Note 11
1
psRMS
Cycle-to-Cycle Jitter
Note 12
1
psRMS
Total Jitter
Note 13
10
psPP
tr, tf
Output Rise/Fall Time (20% to
80%)
At full output swing.
90
200
ps
Output Duty Cycle(÷ 3)
Duty Cycle (input): 50%; f
≤3.2GHz,
Note 14
46
54
%
Output Duty Cycle(÷ 5)
Duty Cycle (input): 50%; f
≤3.2GHz,
Note 14
47
53
%
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
10. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
11. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
12. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
13. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
14. For Input Duty Cycle different from 50%, see “Output Duty Cycle Equation” in “Functional Description” subsection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY89297UMG | ACTIVE DELAY LINE, QCC24 |
| SY89464UMYTR | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| SY89464UMY | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| SY89467UHYTR | 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| SY89467UHY | 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89231UMG TR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89231UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2GHz Precision, LVDS ÷3, ÷5 Clock Divider |
| SY89250V | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ENHANCED DIFFERENTIAL RECEIVER |
| SY89250VMG | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ENHANCED DIFFERENTIAL RECEIVER |
| SY89250VMG TR | 功能描述:緩沖器和線路驅(qū)動(dòng)器 3.3V/5V Ultrasmall Oscillator Amplifier (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。