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參數(shù)資料
| 型號： | SY89295UMI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 標(biāo)片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 3.2ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 3.2ns ~ 14.8ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89295UMITR SY89295UMITR-ND |
Micrel, Inc.
SY89295U
March 2011
13
M9999-032511
hbwhelp@micrel.com or (408) 955-1690
Applications Information
For best performance, use good high-frequency layout
techniques, filter VCC supplies, and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the SY89295U data inputs and outputs.
VBB Reference
The VBB pin is an internally generated reference and is
available for use only by the SY89295U. When unused,
this pin should be left unconnected. Two common uses
for VBB are to handle a single-ended PECL input, and to
re-bias inputs for AC-coupling applications.
If IN and /IN are driven by a single-ended output, VBB is
used to bias the unused input. Please refer to Figure 10.
The PECL signal driving the SY89295U may optionally
be inverted in this case.
When the signal is AC-coupled, VBB is used, as shown
in Figure 13, to re-bias IN and /IN. This ensures that
SY89295U inputs are within acceptable common mode
range.
In all cases, VBB current sinking or sourcing must be
limited to 0.5mA or less.
Setting D Input Logic Thresholds
In all designs where the SY89295U GND supply is at
zero volts, the D inputs can accommodate CMOS and
TTL level signals, as well as PECL or LVPECL. Figures
11, 12 and 14 show how to connect VCF and VEF for all
possible cases.
Cascading
Two or more SY89295U may be cascaded in order to
extend the range of delays permitted. Each additional
SY89295U adds about 3.2ns to the minimum delay and
adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY89295U. Using this internal circuitry, the SY89295U
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY89295U appear in
Figures 7, 8, and 9.
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參數(shù)描述 |
|---|---|
| SY89295UTG | 功能描述:延遲線/計時元素 2.5V/3.3V PECL Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89295UTG TR | 功能描述:延遲線/計時元素 2.5V/3.3V PECL Delay Line (I Temp, Green) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY89295UTGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY |
| SY89295UTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY89295UTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
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