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參數(shù)資料
| 型號(hào)： | SY89296UTG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 3.2ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 3.2ns ~ 14.8ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY89296UTGTR SY89296UTGTR-ND |
Micrel, Inc.
SY89296U
November 2011
13
M9999-112211
hbwhelp@micrel.com or (408) 955-1690
Application Information
For best performance, use good high frequency layout
techniques, filter VCC supplies, and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the SY89296U data inputs and outputs.
VBB Reference
The VBB pin is an internally generated reference and is
available for use only by the SY89296U. When unused,
this pin should be left unconnected. The two common
uses for VBB are to handle a single-ended PECL input,
and to re-bias inputs for AC-coupling applications.
If either IN or /IN is driven by a single-ended output, VBB
is used to bias the unused input. Please refer to Figure
10. The PECL signal driving the SY89296U may
optionally be inverted in this case.
When the signal is AC-coupled, VBB is used, as shown in
Figure 13, to re-bias IN and/or /IN. This ensures that
SY89296U inputs are within acceptable common mode
range.
In all cases, VBB current sinking or sourcing must be
limited to 0.5mA or less.
Setting D Input Logic Thresholds
In all designs where the SY89296U GND supply is at
zero volts, the D inputs can accommodate CMOS and
TTL level signals, as well as PECL or LVPECL. Figures
11, 12, and 14 show how to connect VCF and VEF for all
possible cases.
Cascading
Two or more SY89296U may be cascaded in order to
extend the range of delays permitted. Each additional
SY89296U adds about 3.2ns to the minimum delay and
adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY89296U. Using this internal circuitry, the SY89296U
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY89296U appear in
Figures 7, 8, and 9.
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| SY89295UTG TR | IC DELAY LINE 1024TAP 32-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89296UTI | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY89296UTI TR | 功能描述:IC DELAY LINE 1024TAP 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY89296UTITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY WITH FINE TUNE CONTROL |
| SY89297U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:2.5/3.3V, 3.2Gbps Precision CML |
| SY89297UMG | 功能描述:延遲線/計(jì)時(shí)元素 2.5/3.3V Dual Channel Delay Line with 5ps Step Delay (improved SY89295), Industrial, Recommended for New Designs RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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