Precision Edge SY89429V Micrel, Inc. M9999-011106 hbwhelp@micrel.com or (408) 955-1690 PIN DESCRIPTION" />
參數(shù)資料
型號(hào): SY89429VZH
廠商: Micrel Inc
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 0K
描述: IC SYNTHESIZER PROGR FREQ 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: Precision Edge®
類型: 頻率合成器
PLL:
輸入: 晶體
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 800MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 5.25 V
工作溫度: 0°C ~ 75°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 管件
其它名稱: 576-1422
SY89429VZHC
4
Precision Edge
SY89429V
Micrel, Inc.
M9999-011106
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
INPUTS
XTAL1, XTAL2
These pins form an oscillator when connected to an external
crystal. The crystal is series resonant. See “AN-07” for Crystal
Interface Guideline.
S_LOAD
This TTL pin loads the configuration latches with the contents
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the
HIGH-to-LOW transition of S_LOAD for proper operation.
S_DATA
This TTL pin is the input to the serial configuration shift
registers.
S_CLOCK
This TTL pin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_DATA is sampled.
/P_LOAD
This TTL pin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when this
signal is LOW: Thus, the parallel data must be stable on the
LOW-to-HIGH transition of /P_LOAD for proper operation.
During power up, hold /P_LOAD low with a valid M count on
M[0] - M[8] until supplies have stabilized.
M[8:0]
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of /P_LOAD.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
N[1:0]
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of /P_LOAD.
OUTPUTS
FOUT, /FOUT
These differential positive-referenced ECL signals (PECL)
are the output of the synthesizer.
TEST
The function of this TTL output is determined by the serial
configuration bits T[2:0].
POWER
VCC1
This is the positive supply for the chip and is normally
connected to +3.3V or +5.0V.
VCC_OUT
This is the positive reference for the PECL outputs, FOUT and
/FOUT. It is constrained to be less than or equal to VCC1.
VCC_QUIET
This is the positive supply for the PLL and should be as noise-
free as possible for low-jitter operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
OTHER
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
LOOP_REF
This is an analog I/O pin that provides a reference voltage for
the PLL.
N[1:0]
Output Division
0 0
2
0 1
4
1 0
8
1 1
16
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