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參數(shù)資料
| 型號： | SY89464UMYTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220, MLF-44 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 689K |
| 代理商： | SY89464UMYTR |
Micrel, Inc.
SY89464U
December 2007
M9999-120607-B
hbwhelp@micrel.com or (408) 955-1690
4
Pin Description
Pin Number
Pin Name
Pin Function
2, 5
7, 10
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV
(200mVpp). Each pin of a pair internally terminates to a VT pin through 50
.
Please refer to the “Input Interface Applications” section for more details.
4, 9
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC –1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin.
Bypass with 0.01F low ESR capacitor to VCC. Due to the limited drive capability,
the VREF-AC pin is only intended to drive its respective VT pin. Maximum
sink/source current is ±1.5mA. Please refer to the “Input Interface Applications”
section for more details.
3, 8
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. Please refer to the “Input Interface Applications”
section for more details.
13, 15, 22, 23, 28
33, 34, 41, 43, 44
VCC
Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors as close
to the VCC pins as possible.
40, 39
38, 37
36, 35
32, 31
30, 29
27, 26
25, 24
21, 20
19, 18
17, 16
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Differential Outputs: These differential LVPECL outputs are a logic function of
the IN0, IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
42
SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k
pull-up resistor
and will default to logic HIGH state if left open. VTH = VCC/2.
1, 6, 11
GND,
Exposed Pad
Ground: Ground and exposed pad must be connected to the same ground plane.
12
CAP
Power-On Reset (POR) initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the
internal RPE logic starts up in a known state. See “Power-On Reset (POR)
Description” section for more details regarding capacitor selection. If this pin is
tied directly to VCC, the RPE function will be disabled and the multiplexer will
function as a normal multiplexer. The CAP pin should never be left open or tied
directly to GND.
14
EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9
outputs. It is internally connected to a 25k
pull-up resistor and will default to a
logic HIGH state if left open. When disabled, CLK output goes LOW and /CLK
goes HIGH. EN being synchronous, outputs will be enabled/disabled when they
are in LOW state. Thus, a runt pulse is avoided if the device is enable/disabled
by an asynchronous control. VTH = VCC/2.
Truth Table
Inputs
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
0
1
0
X
0
1
0
X
0
1
0
1
X
1
0
1
0
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