Precision Edge SY89529L Micrel, Inc. M9999-110405 hbwhelp@micrel.com or (408) 955-1690 Input/Output P" />
參數(shù)資料
型號(hào): SY89529LTH TR
廠商: Micrel Inc
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 0K
描述: IC SYNTHESIZER CLK 200MHZ 32TQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: Precision Edge®
類(lèi)型: 時(shí)鐘/頻率合成器
PLL:
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 200MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
4
Precision Edge
SY89529L
Micrel, Inc.
M9999-110405
hbwhelp@micrel.com or (408) 955-1690
Input/Output Pins
Pin Number
Pin Name
I/O
Pin Function
SOIC
TQFP
25,26
8, 9
XTAL1, XTAL2
Analog
These pins form an oscillator when connected to an external
Inputs
crystal. Either series or parallel-resonant crystals are
acceptable. Connect directly to the device.
10, 11
23, 24
SSC Control (0:1)
LVTTL
LVTTL-compatible spread-spectrum control pins. Data on
Inputs
control pins maintain device control. For spread-spectrum
operation, leave SSC_0 and SSC_1 pins floating (default is
spread ON). To reconfigure the device, simply change the
SSC and the device will respond dynamically.
SSC_0 = 24k
pullup. SSC_1 = 24k pulldown
16, 17
30, 31
FOUT, /FOUT
Differential
Differential, LVPECL clock outputs. These outputs must be
terminated to V
CC –2V. (see Figure 6)
23
6
LOOP_FILTER
Analog I/O
Used for the R//C PLL loop filter. (see Figure 2.)
24
7
LOOP_REF
Analog I/O
Provides the reference voltage for the PLL. (see Figure 2).
13
27
TEST INPUT
LVTTL
Pin is used for test and debug purposes. Is intended to be
Inputs
left floating in production environment. Programmed as
input in PLL-bypass mode. Pin includes an internal 24k
pullup resistor.
Power Supply Pins
Pin Number
Pin Name
I/O
Pin Function
SOIC
TQFP
14, 27
10, 28
V
CC1, VCC_TTL
Logic
3.3V LVTTL core logic power-supply pins. Connect each
Power
pin directly to the logic-supply plane and use proper
bypassing at each pin as close to the pin as possible; Ferrite
bead in parallel with 1
F//0.01F capacitors. (see Figure 5
for typical bypass circuit.)
22
5
ANALOG_ V
CC
PLL
3.3V PLL core supply pin. Must be a noise free supply.
Power
Bypass as close to the pin as possible; ferrite bead in
parallel with 1
F//0.01F capacitors. (see Figure 5 for
typical bypass circuit.)
18
32
V
CC_OUT
Output
This is the positive power supply reference for the LVPECL
Power
outputs (FOUT and /FOUT). See Figure 5 for typical bypass
circuit.
12
26
GND_TTL
Logic
This is the ground pin for for the TTL control logic. Normally
connected to the logic ground.
21
4
GND_ANALOG
Analog
This is the ground pin for the PLL Core. Normally connected
GND
to a quiet, noise-free ground plane for low jitter perfomance.
15
29
GND_OUTPUT
Output
Ground for differential outputs. Normally connected to the
GND
logic ground plane.
No Connect Pins
Pin Number
Pin Name
I/O
Pin Function
SOIC
TQFP
1, 2, 3, 4, 5
1, 2, 3, 11, 12, 13
NC
No
Pins are high-impedance, low leakage and are not used by
6, 7, 8, 9, 19
14, 15, 16, 17, 18
Connect
internal circuits of the device. These pins are intended to be
20, 28
19, 20, 21, 22, 25
left floating in production.
PIN DESCRIPTIONS
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