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參數(shù)資料
| 型號： | SY89534LHZTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89534 SERIES, PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 106K |
| 代理商： | SY89534LHZTR |
6
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
AC ELECTRICAL CHARACTERISTICS
TA = 0
°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
fIN
Reference Input Frequency
———
14
—
160
———
MHz
fOUT
Output Frequency Range
———
33.33
—
500
———
MHz
tVCO
Internal VCO Frequency Range
600
—
1000
600
—
1000
600
—
1000
MHz
tskew
Within Device(11)
Within Bank
—
25
50
—
050
—
050
ps
Bank-to-Bank
—
60
150
—
60
150
—
60
150
ps
Part-to-Part Skew(12)
—————
200
——
200
ps
tLOCK
Maximum PLL Lock Time
—————
10
——
10
ms
tJITTER
Cycle-to-Cycle Jitter(13) (Pk-to-Pk)
—————
50
———
ps
Period Jitter(14)
(rms)
——
50
——
50
——
50
ps
tpw (min)
Minimum Pulse Width
———
50
——
50
——
ns
Target PLL Loop Bandwidth
Feedback Divider Ratio: 66(15)
—
1.0
——
1.0
——
1.0
—
MHz
Feedback Divider Ratio: 30(15)
—
2.0
——
2.0
——
2.0
—
MHz
tDC
fOUT Duty Cycle
———
45
50
55
45
50
55
%
tr, tf
Output Rise/Fall Time
ps
(20% to 80%)
LVPECL_Out
——
400
—
250
400
——
400
(SY89535L) LVDS_Out
——
450
—
300
450
——
450
tOUTPUT_RESET
(16)
—————
10
———
ns
tHOLD_FSEL
(16)
———
5
—————
ns
tSETUP_FSEL
(16)
———
5
—————
ns
tOUTPUT_SYNC
(16)
———
1
—————
VCO
clock cycle
FSEL-to-Valid Output Transition Time
————
50
————
ns
All VCC pins = +3.3V ±10%
NOTES:
11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
12. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
13. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn–Tn+1
where T is the time between rising edges of the output signal.
14. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that
signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Parameter guaranteed by
design and characterization.
15. Using recommended loop filter components.
16. See
“Timing Diagrams."
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89535L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER |
| SY89535LHC | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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| SY89535LHHTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER |
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