hbwhelp@micrel.com or (408) 955-1690 6 Pin Descriptio" />
參數(shù)資料
型號(hào): SY89538LHZ
廠商: Micrel Inc
文件頁數(shù): 20/23頁
文件大?。?/td> 0K
描述: IC SYNTHESIZR LVPECL/LVDS 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: Precision Edge®
類型: 時(shí)鐘合成器/扇出緩沖器
PLL:
輸入: CMOS,HSTL,LVDS,LVPECL,LVTTL,SSTL,晶體
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 3:7
差分 - 輸入:輸出: 是/是
頻率 - 最大: 756MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.6 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-EP-TQFP
包裝: 托盤
Micrel, Inc.
SY89538L
January 2008
M9999-010808-E
hbwhelp@micrel.com or (408) 955-1690
6
Pin Description
Input/Output
Pin Number
Pin Name
Pin Function
3, 4
FBIN, /FBIN
External Feedback Input used as the zero delay input. Output feeds into the inputs to
configure the device in zero-delay mode, which forces the output frequency to the
same frequency of the RFCK frequency. Requires external termination. See “Zero
Delay FBIN Input” section for more details.
8, 9
RFCK, /RFCK
Reference Clock Differential Input. Input accepts any input, single-ended or
differential: TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires an
external termination. See “Input Interface” and “Input Termination” sections for more
details.
11, 12
XTAL2, XTAL1
Crystal Input. Directly connect a series resonant crystal across inputs. See “Quartz
Crystal Oscillator Specification” table. Place crystal as close to the input as possible,
keep XTAL and traces away from adjacent noisy traces to minimize noise coupling,
and place the XTAL on the same side as the SY89538L (component side).
17, 18
20, 21
49, 50
52, 53
POUT0, /POUT0
POUT1, /POUT1
POUT2, /POUT2
POUT3, /POUT3
100K LVPECL Output Drivers. Terminate all LVPECL outputs with 50 to VCCO–2V.
Each output pair has a respective output frequency control (PSELx, PENx, DSEL).
See “LVPECL Output Post-Divider and Frequency Select Table” for proper decoding.
For low-jitter applications, unused LVPECL output pairs should be terminated with
pull-down resistors. See “Output Termination Recommendations” section for
termination detail.
38, 39
41, 42
44, 45
LOUT0, /LOUT0
LOUT1, /LOUT1
LOUT2, /LOUT2
Differential LVDS-Compatible Output Drivers. Output termination is 100 across the
pair. For low-jitter applications, unused LVDS output pairs should be terminated with
100 across the pair. See “Output Termination Recommendations” section for
details.
32, 48,
54, 61, 64
NC
No connect.
Input Driver Select Table
RSEL1
RSEL0
Internal Reference
Clock
Zero-Delay
MUX Divider
0
RFCK / 8
FBIN / 8
0
1
RFCK / 4
FBIN / 4
1
0
RFCK / 2
FBIN / 2
1
RFCK / 1
FBIN / 1
Table 1. Reference Input Divider and Zero-Delay MUX Divider Select Table
Pre-Divider Frequency Select Table
PDSEL1
PDSEL0
Pre-Div-Out Frequency
0
(VCO/2) / 5
0
1
(VCO/2) / 4
1
0
(VCO/2) / 3
1
(VCO/2) / 2
Table 2. Pre-Divider Select Table
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