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參數(shù)資料
| 型號： | SY89610LMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER PREC FREQ 32-MLF |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Precision Edge® |
| 類型： | 頻率合成器 |
| PLL： | 是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 694MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，32-MLF? |
| 供應(yīng)商設(shè)備封裝： | 32-MLF?（5x5） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-3088-5 |
Micrel, Inc.
SY89610L
July 2008
4
M9999-071008-D
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
2
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” subsection.
3
VREF-AC
Reference Output Voltage: This output biases to VDD-1.4V. It is used when AC-coupling
the inputs (IN, /IN). Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR
capacitors to VDD. Maximum current source or sink is ±0.5mA. See “Input Interface
Applications” subsection.
4, 5
REFIN,
/REFIN
Differential Input Pair: This input pair is the differential signal input to the device. Input
accepts AC- or DC-coupled differential signals as small as 100mV (200mVPP). Each pin of
this pair internally terminates with 50 to the VT pin. See Figure 1a.
15
/EN
Single-ended Input: This TTL/CMOS input disables and enables the output. It has an
internal pull-down and will default to a logic LOW state if left open. When HIGH, the
output is forced into the disable state (Q = LOW and /Q = HIGH). The pull-down current
is typically 0.5A.
8, 9, 18, 23, 24
GND,
Exposed Pad
Ground: These are the ground pins for core and input stage. Exposed pad must be
connected to a ground plane that is the same potential as the ground pin.
12, 13
CLKOUT,
/CLKOUT
CML Differential Output Pair: Differential buffered output copy of the input signal with very
low jitter. The output swing is typically 400mV. The output pair is referenced to VDDO.
Output pair can be terminated 100 across or 50 to VBIAS. See “CML Output
Termination” subsection.
10
GNDO
Ground: This is the ground pin for output stage. GNDO and GND must be connected
together on the PCB.
11, 14
VDDO
CML Output Driver Power Pins: VDDO enables the output stage to operate from a lower
supply voltage than the core synthesizer voltage. These outputs can be powered from
1.8V ±5% to 3.3V ±10% power supply. For applications that only require 3.3V reference
output operation, VDDO and VDD pins may be connected to a common power supply.
Connect both VDDO pins to same power supply. Bypass with 0.1F//0.01F low ESR
capacitors as close to the VDD pins as possible.
20
RESET
Single-ended Input: Reset is active on the Low-to-High edge of the input pulse. It has an
internal pull-down and will default to a logic LOW state if left open. Resetting the part
starts an auto-tune sequence to provide output frequency closest to input frequency.
Calibration setting is lost on power down. The pull-down current is typically 0.5A.
19
LOL
Single-ended Output: This LVTTL/CMOS output asserts HIGH when the PLL is out of
phase lock. LOL is asserted if the PLL frequency deviates more than ±1000ppm for more
than 5ms. This prevents false triggering. The Loss of Lock pin can be directly connected
to /EN.
27, 26
FILTERP,
FILTERN
Analog Input: These pins provide reference for PLL loop filter. Connect a LOW ESR
capacitor across these pins as close to the device as possible, clear from any supply lines
or adjacent signal lines. See “External Loop Filter Considerations” for loop filter values.
Loop filter capacitor value depends on I/O frequency selection. Loop filter capacitor
layout should include a quiet ground plane under the loop filter capacitor and loop filter
(FILTP, FILTN) pins. Recommend 1206, X5R, 6.3V ceramic type, ±30%. See “PLL Loop
Filter Capacitor Table”.
31
GNDA
Ground: This is an analog ground pin for the PLL. Connect to “quiet” ground. It is
internally referenced to the VCO. GNDA and Ground must be shorted on the PCB.
25, 28, 29
VDDA
Analog Power: Connect to “quiet” 3.3V ±10% power supply. These pins are not internally
connected and must be shorted on the PCB. VDDA internally connects to the VCO.
Bypass with 0.1F//0.01F low ESR capacitors as close to the pin as possible
21, 22
BW0, BW1
Single-ended Input: These LVTTL/CMOS inputs determine the loop bandwidth of the jitter
reducing PLL. BWSEL0 and BWSEL1 will default to a logic HIGH state if left open with a
typical pull-up current of 1.3A. See “Loop Bandwidth Table.”
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89610LMG TR | 功能描述:時鐘合成器/抖動清除器 Precision Frequency Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89610LMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:77.75MHz to 694MHz Jitter Attenuator and Low Phase Noise Frequency Synthesizer |
| SY89645L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision Low Skew, 1-to-4 LVCMOS/LVTTLto-LVDS Fanout Buffer |
| SY89645L_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision Low Skew, 1-to-4 |
| SY89645LK4G | 功能描述:緩沖器和線路驅(qū)動器 1:4 CMOS/LVTTL-to-LVDS Translator+ Fanout Buffer (I Temp, Green) RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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