Precision Edge SY89826L Micrel, Inc. M9999-011907 hbwhelp@micrel.com or (408) 955-1690 PIN DESCRIPTIO" />
參數資料
型號: SY89826LHY TR
廠商: Micrel Inc
文件頁數: 3/10頁
文件大?。?/td> 0K
描述: IC CLK BUF MUX TRNSL 2:22 64TQFP
標準包裝: 1,000
系列: Precision Edge®
類型: 扇出緩沖器(分配),多路復用器,變換器
電路數: 1
比率 - 輸入:輸出: 2:22
差分 - 輸入:輸出: 是/是
輸入: LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 1GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應商設備封裝: 64-EP-TQFP
包裝: 帶卷 (TR)
其它名稱: SY89826LHYTR
SY89826LHYTR-ND
2
Precision Edge
SY89826L
Micrel, Inc.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
PIN DESCRIPTIONS
Internal
Pull-up/
Pin Number
Pin Name
I/O
Type
Pull-down Pin Function
5, 6
LVDS_CLK
Input
LVDS
3.3k
Differential LVDS clock input. Selected when CLKSEL = LOW
/LVDS_CLK
w/100
pull-up
(Can be left floating if CLKSEL = HIGH). This input pair
internal (Figure 2) includes internal termination, and is intended to interface
terminator
directly to LVDS. Leave floating if not used.
8, 9
LVPECL_CLK
Input
LVPECL
75k
Differential LVPECL clock input. Selected when CLKSEL =
/LVPECL_CLK
pull-down HIGH (Can be left floating if CLKSEL = LOW). Requires
(Figure 1) external termination. Leave floating if not used.
7
CLK_SEL
Input
LVTTL/
11k
to Selects LVDS_CLK when LOW and LVPECL_CLK when
CMOS
VCCI
HIGH. Default condition is HIGH if left floating.
11
OE
Input
LVTTL/
Output enable/disable function. When LOW, Q outputs go
LOW, /Q outputs go HIGH. Asynchronous input that is
synchronized internally to prevent output glitches or runt
pulses.
63, 61, 59, 57, 55, 53,
Q0 – Q21
Output
LVDS
Differential LVDS clock outputs when OE = HIGH and static
51, 47, 45, 43, 41, 39,
LOW when OE = LOW. Unused output pairs must be
37, 35, 31, 29, 27, 25,
terminated with 100
across the differential pair to maintain
23, 21, 19, 15
low skew and jitter.
62, 60, 58, 56, 54, 52,
/Q0 – /Q21
Output
LVDS
Differential clock outputs (complement) when OE = HIGH
50, 46, 44, 42, 40, 38,
and static HIGH when OE = LOW. Unused output pairs
36, 34, 30, 28, 26, 24,
must be terminated with 100
across the differential pair to
22, 20, 18, 14
maintain low skew and jitter.
4
VCCI
Power
Core VCC connect to 3.3V supply. Not connected to
VCCO internally. Connect to VCCO on PCB. Bypass
with 0.1
F in parallel with 0.01F low ESR capacitors as
close to VCC pins as possible.
1, 16, 17,
VCCO
Power
Output buffer VCC connects to 3.3V supply. Not connected
32, 49, 64
to VCCI internally. Connect to VCCI on PCB. Bypass
with 0.1
F in parallel with 0.01F low ESR capacitors as
close to VCC pins as possible.
10
GNDI
Power
Core ground not connected to GNDO internally.
Connect to GNDO on PCB.
2, 13, 33, 48
GNDO
Power
Output buffer ground not connected to GNDI internally.
Connect to GNDI on PCB.
3, 12
NC
No connect pins to be left open.
Q1
VCCO
/Q6
Q6
/Q5
Q5
/Q4
Q4
/Q3
Q3
/Q2
Q2
/Q1
/Q0
Q0
VCCO
GNDO
NC
VCCI
LVDS_CLK
/LVDS_CLK
CLK_SEL
LVPECL_CLK
/LVPECL_CLK
GNDI
OE
NC
GNDO
/Q21
Q21
VCCO
GNDO
Q7
/Q7
Q8
/Q8
Q9
/Q9
Q10
/Q10
Q11
/Q11
Q12
/Q12
Q13
/Q13
GNDO
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
/Q19
VCCO
Q14
/Q14
Q15
/Q15
Q16
/Q16
Q17
/Q17
Q18
/Q18
Q19
Q20
/Q20
VCCO
64-Pin TQFP (H64-1)
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89826LHI
H64-1
Industrial
SY89826LHI
Sn-Pb
SY89826LHITR(2)
H64-1
Industrial
SY89826LHI
Sn-Pb
SY89826LHY(3)
H64-1
Industrial
SY89826LHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
SY89826LHYTR(2, 3)
H64-1
Industrial
SY89826LHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
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