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參數(shù)資料
型號: SY89833ALMG
廠商: Micrel Inc
文件頁數(shù): 8/10頁
文件大?。?/td> 0K
描述: IC CLK BUFFER TRANSLA 1:4 16-MLF
產(chǎn)品培訓(xùn)模塊: High Bandwidth Product Overview
標準包裝: 100
系列: Precision Edge®
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
產(chǎn)品目錄頁面: 1083 (CN2011-ZH PDF)
其它名稱: 576-3501-5
Micrel, Inc.
SY88147DL
February 2007
7
M9999-021207-B
hbwhelp@micrel.com or (408) 955-1690
Functional Block Diagram
Detailed Description
The SY88147DL high-sensitivity limiting post amplifier
operates from a single +3.3V power supply, over
temperatures from –40°C to +85°C. Signals with data
rates up to 1.25Gbps and as small as 5mVPP can be
amplified. Figure 1 shows the allowed input voltage
swing. The SY88147DL generates a LOS output,
allowing feedback to /EN for output stability. LOSLVL sets
the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input
stage. The high-sensitivity of the input amplifier allows
signals as small as 5mVPP to be detected and amplified.
The input amplifier allows input signals as large as
1800mVPP. Input signals are linearly amplified with a
typically 42dB differential voltage gain. Since it is a
limiting amplifier, the SY88147DL outputs typically
1500mVPP voltage-limited waveforms for input signals
that are greater than 12mVpp. Applications requiring the
SY88147DL to operate with high-gain should have the
upstream TIA placed as close as possible to the
SY88147DL’s input pins to ensure the best performance
of the device.
Output Buffer
The SY88147DL’s PECL output buffer is designed to
drive 50 lines. The output buffer requires appropriate
termination for proper operation. An external 50
resistor to VCC–2V for each output pin provides this.
Figure 3 shows a simplified schematic of the output
stage.
Loss-of-Signal
The SY88147DL generates a chatter-free loss-of-signal
(LOS) open-collector TTL output with internal 4.75k
pull-up resistor as shown in Figure 4. LOS is used to
determine that the input amplitude is too small to be
considered a valid input. LOS asserts high if the input
amplitude falls below the threshold sets by LOSLVL and
de-asserts low otherwise. LOS can be fed back to the
enable (/EN) input to maintain output stability under a
loss of signal condition. /EN de-asserts low the true
output signal without removing the input signals.
Typically, 3.5dB LOS hysteresis is provided to prevent
chattering.
Loss-of-Signal-Level Set
A programmable LOS level set pin (LOSLVL) sets the
threshold of the input amplitude detection. Connecting
an external resistor between VCC and LOSLVL sets the
voltage at LOSLVL. This voltage ranges from VCC to VREF.
The external resistor creates a voltage divider between
VCC and VREF as shown in Figure 5.
Hysteresis
The SY88147DL typically provides 3.5dB LOS electrical
hysteresis. By definition, a power ratio measured in dB
is 10log (power ratio). Power is calculated as V
2
IN/R for
an electrical signal. Hence, the same ratio can be stated
as 20log (voltage ratio). While in linear mode, the
electrical voltage input changes linearly with the optical
power and hence the ratios change linearly. Therefore,
the optical hysteresis in dB is half the electrical
hysteresis in dB given in the data sheet. The
SY88147DL is an electrical device; this data sheet
refers to hysteresis in electrical terms. With 3.5dB LOS
hysteresis, a voltage factor of 1.5 is required to assert or
de-assert LOS.
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